PPC 975 any truth in this?

[Addison]

On this (http://babelfish.altavista.com/babelfish/tr?doit=done&urltext=http://croquer.free.fr&lp=fr_en) french site is information regarding the supposed successor for the 970. It makes for interesting reading and given that MacBidouille has stopped publishing rumours I wonder if it has any credence.

[tfworld]

Didn't our favorite site, mosr, say this a few weeks ago? :lol:

[Programmer]

They seem to explicitly quote MOSR's "report" (and I use the term loosely) in one of their older blurbs.

The quoted benchmark figures are suspicious... Spec is still only single threaded so how could SMT speed it up? The rest is plausible enough, and to quote Will Smith: I gotta get me one of these!

[tfworld]

How about we wait and see what Apple brings us? Or we can make up ubercool rumors and say they are CONFIRMED!!!

Here is mine:
Dual 3.5Ghz G6 w/ dual cores 8)

[shawk]

This translation may make it clearer.

The IBM PPC 975 will introduce simultaneous multi-threading technology.
The first results from prototypes supplied to Apple are impressive.

Without SMT, a 3 GHz PPC 975 produces a SpecInt 1350 and a SpecFP of 1479.
With SMT, the performance of a 3 GHz PPC 975 increases to a SpecInt of 1650 and a SpecFP of 1750.
This is the twice the performance of a PPC 970 at 2 GHz.

The CPU has 98 million transistors and dissipates 71W at 3GHZ, and 86W at 3,4Ghz.
The Mac G5 975 will be / could be announced at the WWDC and sold some months later.

[fred_lj]

Would this in any way correlate to PowerBook G5s appearing in the same timeframe, albeit underclocked?

[tfworld]

It would need a little more then mearly being underclocked... Maybe drop 50W or so 8)

[Amorph]

Originally posted by shawk
Without SMT, a 3 GHz PPC 975 produces a SpecInt 1350 and a SpecFP of 1479.
With SMT, the performance of a 3 GHz PPC 975 increases to a SpecInt of 1650 and a SpecFP of 1750.

The only possible explanation for this is that someone used IBM's compiler with the option for auto-threading turned on, and somehow it found something to thread.

In a straight compile, the best case is that performance of a single threaded application is no worse with SMT enabled.

I say this is bogus.

[Programmer]

Originally posted by Amorph
The only possible explanation for this is that someone used IBM's compiler with the option for auto-threading turned on, and somehow it found something to thread.

In a straight compile, the best case is that performance of a single threaded application is no worse with SMT enabled.


I'd be doubtful about some kind of auto-threading compiler magic. I suppose the most likely explanation is to run two instances of the SPECs at once and sum their scores. If that's what they did then we can interpret the results as equivalent to having two 825/875 processors in one core (alternatively its one 1350/1480 and one 300/270). This means there is a significant speed hit for using the SMT which is contrary to what IBM's claims for the POWER5 stated (although, to be fair, their claims were specific to a particular problem domain -- not SPEC).

Hmmm... looked at another way, its like having a current G5 sped up by 30-40%, plus a 1+ GHz G4 added in just for good measure.

I'm still not really buying it though... (although if it does ship, I will buy it).

[hasapi]

Looks pretty good, my observations are - for a 970 58million transistors to a 975 98million, and its not dual core, but does have SMT - for an additional 40million transistors?, one explanation could be that the Power5 core is larger than the 970's Power 4 core.

Still, what a bonus to have a 3GHz G5 with supercharger!, I just want the G5's in the iMacs and the Powerbooks! :D

[Outsider]

Originally posted by hasapi
Looks pretty good, my observations are - for a 970 58million transistors to a 975 98million, and its not dual core, but does have SMT - for an additional 40million transistors?, one explanation could be that the Power5 core is larger than the 970's Power 4 core.

Still, what a bonus to have a 3GHz G5 with supercharger!, I just want the G5's in the iMacs and the Powerbooks! :D That is odd. Some things that may increase the transistor size are bigger cache, SMT circuitry, and memory controller.

[Powerdoc]

Originally posted by hasapi
Looks pretty good, my observations are - for a 970 58million transistors to a 975 98million, and its not dual core, but does have SMT - for an additional 40million transistors?, one explanation could be that the Power5 core is larger than the 970's Power 4 core.

Still, what a bonus to have a 3GHz G5 with supercharger!, I just want the G5's in the iMacs and the Powerbooks! :D

The increase of the L2 cache alone represent 20 millions transitors (512000 * 8(bits)* 5 (number of transistors per bit for a static ram)). Add more register, an increase of the L1 cache, SMT circuitry ... and you got it.

[T'hain Esh Kelch]

Originally posted by shawk
This translation may make it clearer.

The IBM PPC 975 will introduce simultaneous multi-threading technology.
The first results from prototypes supplied to Apple are impressive.

Without SMT, a 3 GHz PPC 975 produces a SpecInt 1350 and a SpecFP of 1479.
With SMT, the performance of a 3 GHz PPC 975 increases to a SpecInt of 1650 and a SpecFP of 1750.
This is the twice the performance of a PPC 970 at 2 GHz.

The CPU has 98 million transistors and dissipates 71W at 3GHZ, and 86W at 3,4Ghz.
The Mac G5 975 will be / could be announced at the WWDC and sold some months later.
Originally posted by tfworld
It would need a little more then mearly being underclocked... Maybe drop 50W or so 8)
I would expect these results to be at 0.13 nm.

[shawk]

These results may be for a Power 5. Given the projected production volume and dropping prices, perhaps Apple will use the Power 5 for the pro systems.

[Programmer]

Originally posted by shawk
These results may be for a Power 5. Given the projected production volume and dropping prices, perhaps Apple will use the Power 5 for the pro systems.

The POWER5 doesn't have AltiVec so Apple won't use it. I fully expect there to be a series of 9xx series chips already in the works, however, so don't lose heart... there is a man behind the curtain.

[Programmer]

Originally posted by Powerdoc
The increase of the L2 cache alone represent 20 millions transitors (512000 * 8(bits)* 5 (number of transistors per bit for a static ram)).

Don't forget the control circuitry for the cache as well, it grows with cache size. For the POWER5 IBM quoted a 40% increase in core transistors. If ~20M of the 970 is cache, that would mean a 40% increase in the 38M core... 38M*1.4+20M*2 = ~93M (assuming 1MByte L2). That leaves just 5M unaccounted for in our rather sloppy numbers.

[Yevgeny]

Originally posted by Amorph
The only possible explanation for this is that someone used IBM's compiler with the option for auto-threading turned on, and somehow it found something to thread.

In a straight compile, the best case is that performance of a single threaded application is no worse with SMT enabled.

I say this is bogus.

I agree that this is bogus. Effective auto threading compilers are a pipe dream. Auto threading != SMT