This is getting silly...
<a href="http://news.com.com/2100-1001-882818.html"; target="_blank">http://news.com.com/2100-1001-882818.html</a>;
Intel is coming out next month with a new generation of P4s, with a FSB of 533MHz. Prices on current machines are dropping.
Intel's FSB is now 4 times faster than Apple's, and there is no MHz myth as far as bus speed is concerned, it has been known for a while that the G4s (especially AltiVec) are memory starved.
What we *still* don't know is what Apple is going to do about it. Of course bitching about it here will not do anything. This is not what this thread is here for.
To me, the major problem Macs are facing right now is not the MHz gap, nor the speed of OSX, but the bandwidth starvation.
What do you think would be the best and most plausible move for Apple to make within the next 3 months?
I think a 500MHz RapidIO FSB would be a wise move, if coupled with 266DDR... Supposing of course there aren't any technological obstacles (ie can RapidIO accomodate asynchronous transfers? IIRC, yes).
Let's hope the next generation is worth the wait.
Intel is coming out next month with a new generation of P4s, with a FSB of 533MHz. Prices on current machines are dropping.
Intel's FSB is now 4 times faster than Apple's, and there is no MHz myth as far as bus speed is concerned, it has been known for a while that the G4s (especially AltiVec) are memory starved.
What we *still* don't know is what Apple is going to do about it. Of course bitching about it here will not do anything. This is not what this thread is here for.
To me, the major problem Macs are facing right now is not the MHz gap, nor the speed of OSX, but the bandwidth starvation.
What do you think would be the best and most plausible move for Apple to make within the next 3 months?
I think a 500MHz RapidIO FSB would be a wise move, if coupled with 266DDR... Supposing of course there aren't any technological obstacles (ie can RapidIO accomodate asynchronous transfers? IIRC, yes).
Let's hope the next generation is worth the wait.
Comments
<strong>It seems odd that Apple has let the internal bandwidth "gap" grow and grow. It seems to me that apple should have bumped the bus with the Dual 500's, and I continue to wonder why the are still waiting with the Dual Ghz machines.</strong><hr></blockquote>
Simply because the current G4s only support a 133Mhz bus.
I'd be willing to bet that Apple has fully DDR boards ready to go but with no PowerPC currently supporting it there is no way they can release them.
Hobbled by Moto again <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
<strong>I don't think it's really Moto. They build the processors in accordance to Apples needs. Apple simply hasn't done a good job of forcasting HW changes and having Moto add those changes. They're up against behemoths of Intel and AMD...they'd better put a fire under their arses if they want to compete.</strong><hr></blockquote>
Apple has little or no control over what Moto builds. It's primary markets are embedded controllers and networking, so there really is no desire on the part of Moto to build DDR into a processor who's main use will be in a car or router. 1Ghz is incredibly fast in those areas.
Just look at the Dragonball to see another cpu hobbled by Moto not pushing the limits. Palm are moving to the same processor as PocketPC which is part made by Intel.
RapidIO is a step in the right direction for G4s but again it is for their own benefit, probably in the 3G mobile area. Better Macs are a happy side effect.
I think Apple will have designed the G5 itself for this reason. It might be worked on by Moto engineers too, but I hope it will be a true Mac cpu that can be developed at its own speed.
It's what we need.
The 8500 supports DDR and RapidIO, and it *is* intended for the embedded market...
Is it stated anywhere on Moto's Roadmap when the G4 gets ddr/RapidIO support? If the G4 can support DDR in L3, how come it can't in RAM?
Totally disagree. Apple controls what features they need. Of course there are realworld limits to what Motorola can do but don't think that Apple just "takes" what Motorola can give. PPC instruction set comes from IBM, to which Motorola has added AltiVec, so obviously Apple has more sway than your comments would suggest.
Apple is equally culpable in the sad state of current HW. I ,however, think they will have compelling HW in July. We've waited patiently enough.
2.6 Ghz P4 with a 533MHz bus and 1066Mhz RD-RAM
Subtract
1.6 Ghz G5 with 400Mhz bus and 266Mhz DDR-RAM
what are you left with?
<strong>Apple has little or no control over what Moto builds. It's primary markets are embedded controllers and networking, so there really is no desire on the part of Moto to build DDR into a processor who's main use will be in a car or router. 1Ghz is incredibly fast in those areas.</strong><hr></blockquote>
Yeah right. if Nintendo can get IBM to make a custom 128-bit G3 just for them. I think Apple can get a DDR controller added to the G3/4/5.
[quote]Originally posted by Blackcat:
<strong>Just look at the Dragonball to see another cpu hobbled by Moto not pushing the limits. Palm are moving to the same processor as PocketPC which is part made by Intel.</strong><hr></blockquote>
The DragonBall(and the Palm it sits in) is a piece of garbage.
And the StrongARM was designed jointly by Acorn, Digital Equipment and Apple. plus it's also the same processor as <a href="http://www.nokiausa.com/communicator/features/1,4769,,00.html"; target="_blank">Symbian/EPOC</a> uses.
The first to (Kind of)go was Acorn. who just upped and spun off the ARM/StrongARM division, then Apple left when Jobs killed the Newton. but DEC only surrendered ARM to Intel when it was practically forced to do so in a fishy out of court settlement of Intel stealing DEC Alpha technology in a breach of contract and sticking it in their (Suspiciously faster)Pentium II.
[quote]Originally posted by Blackcat:
<strong>RapidIO is a step in the right direction for G4s but again it is for their own benefit, probably in the 3G mobile area. Better Macs are a happy side effect.</strong><hr></blockquote>
3G mobile area <img src="graemlins/lol.gif" border="0" alt="[Laughing]" /> . you could run several 3G connections off a USB port!
RapidIO is more like a PCI replacement(Plus you can make clusters with it
[quote]Originally posted by Blackcat:
<strong>I think Apple will have designed the G5 itself for this reason. It might be worked on by Moto engineers too, but I hope it will be a true Mac cpu that can be developed at its own speed.</strong><hr></blockquote>
I doubt it. the G5 is practically entering production already. stick a fork in it. it's done.
Eric,
[ 04-16-2002: Message edited by: Eric D.V.H ]</p>
<strong>Take
2.6 Ghz P4 with a 533MHz bus and 1066Mhz RD-RAM
Subtract
1.6 Ghz G5 with 400Mhz bus and 266Mhz DDR-RAM
what are you left with?</strong><hr></blockquote>
A really fast out of date Mac <img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
[quote]Originally posted by JasonPP:
<strong>Take
2.6 Ghz P4 with a 533MHz bus and 1066Mhz RD-RAM
Subtract
1.6 Ghz G5 with 400Mhz bus and 266Mhz DDR-RAM</strong><hr></blockquote>
Take a quick read through <a href="http://rapidio.org/tech/"; target="_blank">this</a>(For the bus) and <a href="http://www.mackido.com/Hardware/rdram.html"; target="_blank">this</a>(For the RAM).
[quote]Originally posted by JasonPP:
<strong>what are you left with?</strong><hr></blockquote>
Intel's bloody, battered remains.
Eric,
[ 04-16-2002: Message edited by: Eric D.V.H ]</p>
<strong>
The 8500 supports DDR and RapidIO, and it *is* intended for the embedded market...
</strong><hr></blockquote>
True, but I think thats because RapidIO makes DDR a 'freebie' and RIO is very useful in a controller to keep component count low.
[quote]
<strong>
Is it stated anywhere on Moto's Roadmap when the G4 gets ddr/RapidIO support? If the G4 can support DDR in L3, how come it can't in RAM?</strong><hr></blockquote>
The 7500 is alleged to have it, and may well be the G5.
I think the G4 has DDR L3 because your average embeded device needs very fast operation but no actual RAM.
Along the time the B&W G3s came, Apple was not only competitive with the x86 world, but also had a real and global performance edge.
Within 9 months, Apple unleashed the PowerMacG4, and supply problems appeared immediately, along with a deeper, bigger problem: scalability.
Looking back, one can legitimately wonder what AIM has been doing ever since. IBM is still working on the G3 and remarkably so, and Motorola is turning out minor speed-bumps and revs to the G4. What has Apple been doing?
Apple came out with the MPG4s, clocked at 500MHz, less than a year after the release of the original G4s. Thus, Apple *knew* when the supply problem became apparent, that it would be a while before Moto could turn out faster chips.
So what did Apple do, what did Jobs, Rubinstein and even Tevanian (OSX is clearly geared towards current gen hardware, which should have been out according to Moore's law arond the time OSX came out) say to Somerset when it became apparent that the G4 was born without legs?
My guess is as follows: Development of a new CPU architecture takes give or take 18 months (correct me if I'm wrong gere) for a company the size of Motorola. Development of a new CPU architecture, with parallel development of current gen CPU in order to scale it, add AltiVec units, double frequency, shrink die size, would take significantly longer. Thus AIM is sitting on a brand new rev of the PPC architecture. I'm not saying it is going to a brand-new architecture, like some reports of G5 performance have been saying, but a significant update to current architecture in order to bring it up to date, and make it competitive.
Apple knew this CPU would be ready around 3 years after the infamous G4-debacle. So Rubinstein probably gave Sumerset a tech sheet detailing what he wanted. What this tech sheet had is what we need to know. My (uneducated) guess, would be more scalability, enhanced FPU, 64bit capable in a later rev (remember at that time the Itanium was very much hyped), enhanced and more powerful AltiVec (perhaps even making it programmable, ala GF3), AND an overhauled FSB architecture (remember at that time, the Athlon with its 200MHz bus was around the corner, and no one would have guessed the Athlon would still be at 266MHz). In most of his speeches, Rubinstein emphasizes the importance of overall system performance. This is also probably the reason why we've seen large L3 caches, he knows the current bus was not designed to scale to current speeds.
Therefore, I definitely think we'll be seeing a mobo overhaul soon. FSB speeds will be around those of Intel's. We will probably see, when the market is ready, serial-ATA, FireWire2, support being already in the mobo architecture.
Whether or not this machine will be ready for MWNY is anyone's guess. Perhaps the stealth release of the current generation is an indication to the imminent (as in within 6 months) release of the next gen.
I want to believe
Take
2.6 Ghz P4 with a 533MHz bus and 1066Mhz RD-RAM
Subtract
1.6 Ghz G5 with 400Mhz bus and 266Mhz DDR-RAM
what are you left with? <hr></blockquote>
A negative. <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
Mattyj - "negative" - ha ha lol!
Long live the RDF...
[ 04-16-2002: Message edited by: JasonPP ]</p>
Ouch!
Lemon Bon Bon
OUCH! Smash volley.
I'm really looking forward to the G5.
'Who's the DADDY!?"
Lemon Bon Bon
Yeah right. if Nintendo can get IBM to make a custom 128-bit G3 just for them. I think Apple can get a DDR controller added to the G3/4/5.</strong>
The Gekko PowerPC in Nintendo GameCubes is a slightly tweaked IBM PowerPC 750cx. There's nothing 128 bit about them. The three main tweaks were changing the FPU to do 2 32 bit floating point ops, adding some SIMD instructions to use said change to the FPU, and running the 64 bit data 32 bit address processor bus at higher clock rates.
The initial GameCube had a processor bus clock rate of about 202 MHz with the processor running 405 MHz, and the second version has a processor bus clock rate of 162 MHz (it was lowered) and a processor clock rate of 485 MHz. The magic in the GameCube are specialized SRAM-like DRAM memory from MoSys (1T-SRAM) and the graphics chip, all outside of the PowerPC. Apple really doesn't have this option.
It is curious that DDR hasn't been designed into the MPX bus yet, especially with a tweaked 7455, but I suspect Motorola just doesn't want to put the core logic investment into supporting it, especially since PPC chips with on-die DDR SDRAM controllers are on the horizon. They don't even, perhaps barely, support the MPX bus itself.
<strong>I read the links.. Rapid IO is out of context and the Makido link is from 1999 it seems. Maybe I should check Marthastwart.com for better links?
Mattyj - "negative" - ha ha lol!
Long live the RDF...</strong><hr></blockquote>
(BTW: I read <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655"; target="_blank">Motorola's page on the PPC 8540</a>. just like I thought. the DDR 2600 is connected through it's own dedicated bus. and the RapidIO is just used like PCI)
The <a href="http://www.mackido.com/Hardware/rdram.html"; target="_blank">MacKiDo link</a> is old. but still true. it demonstrates that all is not as it seems by using the following formula:
(Bit depth)x(Clock frequency)=(True speed in <a href="http://www.webopedia.com/TERM/M/Mbps.html"; target="_blank">Mbps</a>)÷8=(True speed in <a href="http://www.webopedia.com/TERM/M/MBps_megabytes.html"; target="_blank">MBps</a>)
Thusly:
- PC133 SDRAM(The stuff in the G4s of today):
- RDRAM 1066(The stuff in the P4s of today):
- DDR SDRAM 133(The stuff that you thought is in the G5):
- DDR SDRAM 333(The stuff that's <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655"; target="_blank">in the G5</a>):
Translation:64-bitsx133Mhz=8512Mbps÷8=1064MBps
16-bitsx1066Mhz=17056Mbps÷8=2132MBps
64-bitsx266Mhz=17024Mbps÷8=2128MBps
64-bitsx333Mhz=21312Mbps÷8=2664MBps
The 266Mhz DDR that you thought is in the G5 is near identical in true speed to the new Pentium 4's 1066Mhz RDRAM. and The <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655"; target="_blank">333Mhz DDR that's ACTUALLY in the G5</a> whups Intels hide.
And I was using the <a href="http://rapidio.org/tech/"; target="_blank">RapidIO link</a> to point out that RapidIO isn't a RAM bus(Not to be confused with Rambus
While not as fast(Or as long on the market) as <a href="http://www.hypertransport.org/"; target="_blank">HyperTransport</a>. it features an InfiniBand-like capability to connect multiple computers or other devices together. it's also faster than any form of PCI, AGP or InfiniBand(Even PCI-X and AGP 8x). Oh yeah. there's also Intel's highly theoretical 3GIO which. while faster than RapidIO. is beaten by HyperTransport. 3GIO is slated to replace PCI. <a href="http://forums.appleinsider.com/cgi-bin/ultimatebb.cgi?ubb=get_topic&f=1&t=001359&p="; target="_blank">I hope it doesn't</a>.
Eric,
[ 04-17-2002: Message edited by: Eric D.V.H ]</p>