I'm looking to show my friend information on why the 980 will be radically different than the 970. Any links or information I can show him?
Also any good article on how the 970 works (the ars one is only half good)
Thanks.
Wow, I'm impressed- Hannibal's best effort's good enough to get used by IBM themselves, but only "half good" enough to show your friend- who the heck is he?
I'm looking to show my friend information on why the 980 will be radically different than the 970. Any links or information I can show him?
Also any good article on how the 970 works (the ars one is only half good)
Thanks.
There is no evidence there even IS a 980. It's just rumour and conjecture based on IBM saying that this was the first in a new family of processors.
There has been no evidence that any future processor will be based on the power 5. It's likely, but there's no evidence
There is no evidence that any future processor will be called the 980, or what this might represent- maybe the die shrunk 970 will become a 980.
You've just had a spanking brand new processor that brings Apple back into the game. What more do you want? Expecting anything else as revolutionary (for Apple) as the 970 in the next year is bound to lead to dissapointment. Speed increases yes, a new processor, no.
Hmmm. I just searched for IBM 980 POWER5 and it was sobering to see the paucity (read: absence) of reliable or semi-reliable info. The page that I liked best was essentially a compendium of various rumours, without any pretenses to the contrary.
FWIW, I strongly suspect that the 980 (presuming there will be a "POWER5 lite") will have more in common with the POWER5 than the 970 has with the POWER4. I'm too lazy to do more searches on this topic, but I do recall official claims that the POWER5 will feature at least some additional instructions for specialised functions -- rather like Altivec. Moreover, the POWER5 is intended to be a less expensive chip than the POWER4, one that will scale up to big iron, as opposed to being a big iron chip that can be scaled down.
I'm personally confident that there will be a 980-ish chip eventually, simply because it makes little business sense for IBM not to produce such a thing. Once the POWER5 has been developed, deriving a desktop variant is pretty much money for jam.
IBM has said in one or two press articles that they key changes in the POWER5 are:
- Aimed at lower end hardware than POWER4.
- Targetting significantly higher clock rates.
- The addition of what they call "FastPath" acceleration for key OS functions (like the network stack). This is not like AltiVec, it is more like asynchronous DMA hardware that has logic built into it.
- The addition of simultaneous multithreading which is like Intel's HyperThreading, except better.
I expect we'll see a future 9x0 chip based on the POWER5 technology, but next year seems a bit optimistic for it. We may also see something more directly based on the 970 with some of the same elements added (i.e. SMT).
Besides, John E. Kelly of IBM stated clearly that IBM has already the prototypes of the next generation PPC processor. Guess where he said that: in the G5 introduction movie. For me this is a strong evidence that we will see another PPC processor (for desktops) by late 2004 or beginning 2005. Simply we don't know what exactly could be. Hopefully, this years MPF will show more.
The chief editor of microprocessor report, (sorry forget his name) said that he was impressed by the new PPC 970. He said that the the die size of this chip was pretty good : 118 square millimiter, and there is great chance to see a 1 or 2 MB cache when 0,09 micron process will be avalaible : the PPC 970 +.
Such increse of the L2 cache, will be a great improvement in itself.
- The addition of what they call "FastPath" acceleration for key OS functions (like the network stack). This is not like AltiVec, it is more like asynchronous DMA hardware that has logic built into it.
Thanks for the clarification! Am I to take it that there won't be any new instructions associated with this, given what we've been told?
Thanks for the clarification! Am I to take it that there won't be any new instructions associated with this, given what we've been told?
There will be some new control mechanism for the hardware, and it might be memory-based, register-based, or instruction-based. Given the typical PowerPC approach to this kind of thing, I would guess register-based (MSRs, machine specific registers).
On the existance of the 980: the best evidence for this is on the IBM Microelectronics website there is a pull down menu labelled "9xx 64-bit microprocessors". They have also stated that the 970 "is the first in a new series of PowerPC processors". Since companies tend to number things sequentially I'd say that a 980 is a good bet.
While this comment doesn't totally fit to this topic, I really don't wish to start "YA970" thread...
The 970 is here, and here for awhile. Don't expect the 980 [whatever it will be called] to arrive far after the POWER5 chip is up and running in full production status.
This leaves us to the future of the 970. IBM and Jobs has said "3 Gig in 12 months" ...this points to an obvious die shrink to 90nm [.09 micrometer]. Neither IBM, nor Apple would be satisfied with the same exact chip, just smaller. So what's on board?
Judging from posts by Mr. NSX over at Ars' Mac Ach, the 970 was in the design phase for 3 years or so. That seems to hold up when looking at the 970 Altivec unit. [For those that don't know what I am talking about, the 970 Altivec unit is the same one that is in the 7400 and 7410 G4 processors.] My thoughts are that we'll see a more mature Altivec unit when the 970 goes 90nm. The unit will be either a clone of the more modern G4s, or the next evolutionary step passed them. This should boost the 970 Altivec performance to "better-than-clock-for-clock" with the G4.
I'd like to see an on-chip memory controller, but for some reason, I don't think we will at this time. I suspect that will hold off until the 980, as doing so would totally change the current MLB design. It would however, make it cheaper to produce. Hmmm. My vote is still no on-chip memory controller.
Cache! The new "750FX" chips that will be testing shortly will have a 1MB L2 cache. That's *huge*. This also helps the memory starved 750 from spinning its wheels waiting for data. Remember, the new G3 will only have a 200MHz FSB, single pumped. The 970s [and the G5s they are in] are a different beast. They *have* the bandwidth to keep up, so I am not sure if the extra cost of additional cache would be worth the speed trade-off. Cache takes up *massive* amounts of room on the die, room that could be taken up for things like additional ALU, FPU, VPU.
So what are your thoughts? Always interested to hear.
I agree that it isn't a bad idea to do more with the chip than just shrinking it. 1MB of L2 cache is always good, good bandwidth is not always the solution to the problems. Cache misses always slows down, and L2 cache has alot less latency than main memory. A larger L2 would keep cache-misses down, and keep the pipelines full. However, integer performance is the 970's weak spot, it seems, and an additional ALU would maybe be good use of extra silicon, but I suspect the R&D for such a unit would require alot of time, and maybe push the schedule for the .09µ version back.
I agree that it isn't a bad idea to do more with the chip than just shrinking it. 1MB of L2 cache is always good, good bandwidth is not always the solution to the problems. Cache misses always slows down, and L2 cache has alot less latency than main memory. A larger L2 would keep cache-misses down, and keep the pipelines full. However, integer performance is the 970's weak spot, it seems, and an additional ALU would maybe be good use of extra silicon, but I suspect the R&D for such a unit would require alot of time, and maybe push the schedule for the .09µ version back.
You are right, L2 cache have much lower latencie, and is wider than the main memory (256 bit full speed, versus 128 bit 400 mhz DDR ram).
If we look at the evolution of the chip of various companies, we see that the L2 cache size is getting bigger and bigger after each generations. For example the centrino chip is an improved Pentium 3 design with SSE2 and a one mb cache , and it rocks, and smoke a pentium 4 at equal mhz.
There is no competition between L2 cache and main memory. There is competition between L3 cache and main memory. As the bus and the main memory of the PPC 970 is huge, i doubt that they will ever appear a L3 cache.
In other way, a L2 cache will bring advantages. A one MB L2 cache ppc 970 on 90 nm process looks logical.
I am still not quite convinced that the 970+ will have extra cache. I don't think the die shrink will allow for it [takes too much room on the die, and the expense of 90nm RAM would make it too expensive]. That said, I *do* think they will find a way to re-position the caches [L1 and L2] so there is less latency in the cache-line. Currently, the 970 cache-line latency is more than that of the G4. Of course, I don't quite know if the latency is due to the 128bit path, or physical location, so the previous postulation may be moot.
As for L3 cache, As it stands, the 970 doesn't have the ability to accept a traditional L3 cache. Yes, this can change with the die shrink, but I don't think the trade-off is cost effective [for the performance gain]. This of course, does not preclude the addition of a "hacked on" L3, as described in various other threads, where the cache is actually memory-controller cache. In this situation, I am not sure it will be cost effective either, but who knows. Perhaps the EBus will need it in order to prevent data-starvation. A 1.5GHz bus is a monster, and I don't think DDR RAM is capable of keeping pace. Of course, by that time DDRII should be available [pray!] and may alleviate some of the bottleneck.
There is a typical "ideal physical size" for a microprocessor, and the current 970 is about right on. A 0.09 micron version would be smaller and thus sub-optimal in terms of physical size, so I would be surprised if they did not increase the cache to consume the extra space.
One another note: the 970 does not have "the same" AltiVec unit as the 7400/7410. It is similar in number of execution units, but it is a completely new unit designed specifically for the 970. Its characteristics don't even match the 74x0 exactly, they are just closer to the 7400 than to the 745x.
There is a typical "ideal physical size" for a microprocessor, and the current 970 is about right on.
Programmer, I am not saying you are wrong but, why do you say there is an ideal size and what is it? I have never heard that before not that I know any better.
Comments
Originally posted by inkhead
I'm looking to show my friend information on why the 980 will be radically different than the 970. Any links or information I can show him?
Also any good article on how the 970 works (the ars one is only half good)
Thanks.
IBM has some great PDF's on the 970. Check some of the recent 970 links on this page. I think one good pdf is attached by MartianMatt.
There is no info on the 980. It's totally vapor right now. IBM won't even give much info on the POWER5 which the 980 should be based on.
Originally posted by inkhead
I'm looking to show my friend information on why the 980 will be radically different than the 970. Any links or information I can show him?
Also any good article on how the 970 works (the ars one is only half good)
Thanks.
Wow, I'm impressed- Hannibal's best effort's good enough to get used by IBM themselves, but only "half good" enough to show your friend- who the heck is he?
Originally posted by inkhead
I'm looking to show my friend information on why the 980 will be radically different than the 970. Any links or information I can show him?
Also any good article on how the 970 works (the ars one is only half good)
Thanks.
There is no evidence there even IS a 980. It's just rumour and conjecture based on IBM saying that this was the first in a new family of processors.
There has been no evidence that any future processor will be based on the power 5. It's likely, but there's no evidence
There is no evidence that any future processor will be called the 980, or what this might represent- maybe the die shrunk 970 will become a 980.
You've just had a spanking brand new processor that brings Apple back into the game. What more do you want? Expecting anything else as revolutionary (for Apple) as the 970 in the next year is bound to lead to dissapointment. Speed increases yes, a new processor, no.
FWIW, I strongly suspect that the 980 (presuming there will be a "POWER5 lite") will have more in common with the POWER5 than the 970 has with the POWER4. I'm too lazy to do more searches on this topic, but I do recall official claims that the POWER5 will feature at least some additional instructions for specialised functions -- rather like Altivec. Moreover, the POWER5 is intended to be a less expensive chip than the POWER4, one that will scale up to big iron, as opposed to being a big iron chip that can be scaled down.
I'm personally confident that there will be a 980-ish chip eventually, simply because it makes little business sense for IBM not to produce such a thing. Once the POWER5 has been developed, deriving a desktop variant is pretty much money for jam.
- Aimed at lower end hardware than POWER4.
- Targetting significantly higher clock rates.
- The addition of what they call "FastPath" acceleration for key OS functions (like the network stack). This is not like AltiVec, it is more like asynchronous DMA hardware that has logic built into it.
- The addition of simultaneous multithreading which is like Intel's HyperThreading, except better.
I expect we'll see a future 9x0 chip based on the POWER5 technology, but next year seems a bit optimistic for it. We may also see something more directly based on the 970 with some of the same elements added (i.e. SMT).
Such increse of the L2 cache, will be a great improvement in itself.
Originally posted by Programmer
- The addition of what they call "FastPath" acceleration for key OS functions (like the network stack). This is not like AltiVec, it is more like asynchronous DMA hardware that has logic built into it.
Thanks for the clarification! Am I to take it that there won't be any new instructions associated with this, given what we've been told?
We know that Power 4 -> 970, but has anyone confirmed the Power 5 -> 980.
Originally posted by Ompus
Am I correct that there is no authoritative evidence that IBM wil EVER make a 980?
We know that Power 4 -> 970, but has anyone confirmed the Power 5 -> 980.
no.
Originally posted by boy_analog
Thanks for the clarification! Am I to take it that there won't be any new instructions associated with this, given what we've been told?
There will be some new control mechanism for the hardware, and it might be memory-based, register-based, or instruction-based. Given the typical PowerPC approach to this kind of thing, I would guess register-based (MSRs, machine specific registers).
On the existance of the 980: the best evidence for this is on the IBM Microelectronics website there is a pull down menu labelled "9xx 64-bit microprocessors". They have also stated that the 970 "is the first in a new series of PowerPC processors". Since companies tend to number things sequentially I'd say that a 980 is a good bet.
Originally posted by applenut
no.
I thimh that should be yes, no.
The 970 is here, and here for awhile. Don't expect the 980 [whatever it will be called] to arrive far after the POWER5 chip is up and running in full production status.
This leaves us to the future of the 970. IBM and Jobs has said "3 Gig in 12 months" ...this points to an obvious die shrink to 90nm [.09 micrometer]. Neither IBM, nor Apple would be satisfied with the same exact chip, just smaller. So what's on board?
Judging from posts by Mr. NSX over at Ars' Mac Ach, the 970 was in the design phase for 3 years or so. That seems to hold up when looking at the 970 Altivec unit. [For those that don't know what I am talking about, the 970 Altivec unit is the same one that is in the 7400 and 7410 G4 processors.] My thoughts are that we'll see a more mature Altivec unit when the 970 goes 90nm. The unit will be either a clone of the more modern G4s, or the next evolutionary step passed them. This should boost the 970 Altivec performance to "better-than-clock-for-clock" with the G4.
I'd like to see an on-chip memory controller, but for some reason, I don't think we will at this time. I suspect that will hold off until the 980, as doing so would totally change the current MLB design. It would however, make it cheaper to produce. Hmmm. My vote is still no on-chip memory controller.
Cache! The new "750FX" chips that will be testing shortly will have a 1MB L2 cache. That's *huge*. This also helps the memory starved 750 from spinning its wheels waiting for data. Remember, the new G3 will only have a 200MHz FSB, single pumped. The 970s [and the G5s they are in] are a different beast. They *have* the bandwidth to keep up, so I am not sure if the extra cost of additional cache would be worth the speed trade-off. Cache takes up *massive* amounts of room on the die, room that could be taken up for things like additional ALU, FPU, VPU.
So what are your thoughts? Always interested to hear.
Originally posted by Zapchud
I agree that it isn't a bad idea to do more with the chip than just shrinking it. 1MB of L2 cache is always good, good bandwidth is not always the solution to the problems. Cache misses always slows down, and L2 cache has alot less latency than main memory. A larger L2 would keep cache-misses down, and keep the pipelines full. However, integer performance is the 970's weak spot, it seems, and an additional ALU would maybe be good use of extra silicon, but I suspect the R&D for such a unit would require alot of time, and maybe push the schedule for the .09µ version back.
You are right, L2 cache have much lower latencie, and is wider than the main memory (256 bit full speed, versus 128 bit 400 mhz DDR ram).
If we look at the evolution of the chip of various companies, we see that the L2 cache size is getting bigger and bigger after each generations. For example the centrino chip is an improved Pentium 3 design with SSE2 and a one mb cache , and it rocks, and smoke a pentium 4 at equal mhz.
There is no competition between L2 cache and main memory. There is competition between L3 cache and main memory. As the bus and the main memory of the PPC 970 is huge, i doubt that they will ever appear a L3 cache.
In other way, a L2 cache will bring advantages. A one MB L2 cache ppc 970 on 90 nm process looks logical.
As for L3 cache, As it stands, the 970 doesn't have the ability to accept a traditional L3 cache. Yes, this can change with the die shrink, but I don't think the trade-off is cost effective [for the performance gain]. This of course, does not preclude the addition of a "hacked on" L3, as described in various other threads, where the cache is actually memory-controller cache. In this situation, I am not sure it will be cost effective either, but who knows. Perhaps the EBus will need it in order to prevent data-starvation. A 1.5GHz bus is a monster, and I don't think DDR RAM is capable of keeping pace. Of course, by that time DDRII should be available [pray!] and may alleviate some of the bottleneck.
just my .02
One another note: the 970 does not have "the same" AltiVec unit as the 7400/7410. It is similar in number of execution units, but it is a completely new unit designed specifically for the 970. Its characteristics don't even match the 74x0 exactly, they are just closer to the 7400 than to the 745x.
Originally posted by Programmer
There is a typical "ideal physical size" for a microprocessor, and the current 970 is about right on.
Programmer, I am not saying you are wrong but, why do you say there is an ideal size and what is it? I have never heard that before not that I know any better.