PowerBook Cache downgraded???!!!
Hey! Didn't the PB's have L3 cache? What happened??? Why are they at L2 now??? Am I missing something? Does anyone know what's going on? Is this a bad thing, or good? I am by no means a computer whiz, but this seems like they just downgraded the cache... maybe to fix heating issues???
Or maybe it's not that big a deal... anyone know???
Or maybe it's not that big a deal... anyone know???
Comments
One school of thought says that's it's a cost-cutting measure that will diminish performance, the other argues that with the increase in CPU, FSB and L2 speed things'll be okay.
Frankly we'll just have to way until some legitimate benchmarks appear.
1.33 GHz, 512k l2, 167 MHz path to RAM.
Woulda been nice if they still had the l3 since the original intention of the l3 was to make up for the FSB bottleneck...which is still there.
Originally posted by vraxtus
Isn't it 512k full speed cache? And I wouldn't worry that much about the L3 cache missing.
Yes it is. Outsider's just taking into account that it's an additional 256K. I would worry because the L3 cache was to make up for the lack of fast access to the main system RAM and not the amount of L2 cache.
Originally posted by RANSOMED
Hey! Didn't the PB's have L3 cache? What happened??? Why are they at L2 now??? Am I missing something? Does anyone know what's going on? Is this a bad thing, or good? I am by no means a computer whiz, but this seems like they just downgraded the cache... maybe to fix heating issues???
Or maybe it's not that big a deal... anyone know???
Cache is essentially a buffer to hold information. In the case of processor cache, it serves to hold data that is either waiting to be processed by the CPU, or is on the way out of the CPU.
In order of importance and benefit, the very best cache is L1, the "worst" would be L3. When I'm talking about good vs. bad, it's in very relative terms.
L1 cache is integrated onto your processor die in a very integral way, my understanding of this is that it has extremely high bandwidth, the fastest access times (lowest latency), and is the most expensive per kilobyte. This cache holds instructions that are soon to be executed by the processor, as well as outbound data.
L2 cache is the next step between your CPU registers and main system RAM. A bit cheaper per kilobyte, higher latency, and lower bandwidth. Note that this is often still integrated on the the processor die, so runs at the full speed of your CPU.
L3 cache is the last buffer between your CPU and system RAM. Cheapest per kilobyte, lower bandwidth, higher latency. L3 usually runs at 1/2 your CPU speed at best, and as mentioned above in this thread, is one way of helping to compensate for slower FSBs (system Front Side Buses) that are the interface between your CPU, RAM, video, I/O, etc.
The importance of cache is that it isn't yet feasible to run your system buses as fast as the internal clock on a CPU, which causes there to be gaps (waits) while the CPU is waiting for more information to process. Think of it as a fire truck that you have to feed water into bucket by bucket - it can only spray as much water as you put in by hand, even though it's capable of much greater water output.
On the Wintel side of the industry, the most noticeable benefit from the addition of on-die L2 cache was with the "Mendocino" line of the Intel Celeron processors. The previous models had no L2 or L3 cache, but when Intel equipped the Celeron with 256K (I think it was) of L2 cache built into the CPU die, it suddenly was easily the match of a similarly clocked Pentium II. Full speed, on-die cache is (was) also conducive to overclocking.
Sorry if any of the above is garbled, I'll blame it on being tired.
Originally posted by Chagi
Sorry if any of the above is garbled, I'll blame it on being tired.
On the contrary, it was quite lucid. Thank you.
according to these benchmarks the missing L3 cache hasn't hampered performance too much.
I site this as a cost cutting measure. I'm sure Apple benchmarked the new G4s and found they are close in performance to the L3/G4 and saved the money.
Originally posted by hmurchison
http://www.barefeats.com/al15.html
according to these benchmarks the missing L3 cache hasn't hampered performance too much.
I site this as a cost cutting measure. I'm sure Apple benchmarked the new G4s and found they are close in performance to the L3/G4 and saved the money.
Cost is a possibility, but I also have a gut feeling that the issue runs deeper. Could be possible that good old Motorolla was having problems getting L3 caches up to higher speeds.
Again, drawing on my PC experience, I seem to recall that the Pentium II line was often difficult to overclock. This was not due to the chip itself, but was often due to the ability of the off die L2 cache to overclock. The external cache chips were rated to a certain speed, at which point they started becoming unstable if pushed to high.
I'm speculating here, but given Motorolla's repeated inability to ramp the clockspeeds of the G4, it could be a factor in their decision to remove the L3.
In the new 15" Al PB there is no L3 cache. The L2 cache runs at 1.25GHz and the system bus is 167MHz.
Recap: The new PB has twice as much L2 cache running twice as fast as before and the system bus is about 25% faster. This should go a long way towards mitigating the bus bottleneck.
Certainly there are room for improvements. Why not 1MB of L2 cache? Why not 2MB of L3 cache at more than 200MHz?
I think that Apple evaluated the alternatives and decided that L3 cache in this system running at 167MHz was too costly and used too much power for the benefit it returned.
Motorola's 7457: JUST AS SHIT
They both have crappy cache in different ways! Yay for Motorola!
But seriously, yeah it's still bad BUT the notebooks still rock. It's not like any of you would use the performance of a G5. The upgraded graphics chip should compensate for any loss of performance in that side of things too.
Barto
Originally posted by neutrino23
In the Ti PB the L3 cache ran at 133MHz. The L2 cache for the 1GHz Ti PB ran at 667MHz and the system bus was 133MHz.
In the new 15" Al PB there is no L3 cache. The L2 cache runs at 1.25GHz and the system bus is 167MHz.
Recap: The new PB has twice as much L2 cache running twice as fast as before and the system bus is about 25% faster. This should go a long way towards mitigating the bus bottleneck.
Certainly there are room for improvements. Why not 1MB of L2 cache? Why not 2MB of L3 cache at more than 200MHz?
I think that Apple evaluated the alternatives and decided that L3 cache in this system running at 167MHz was too costly and used too much power for the benefit it returned.
Interesting, I didn't notice that 12" and 15"/17" used different FSB speeds. Looks like the 12" uses a 133MHz FSB, with PC 2100 DDR (266MHz) DDR RAM. Btw, for those that don't know DDR is "Double Data Rate" RAM, basically doubled the speed of circuit access/refresh compared to older RAM.
As for the reason we're not seeing larger L2 and/or L3 with the new models comes down to money. Apparently L2 cache design gets more difficult the higher you go in size, leading to larger numbers of rejects, as well as greater cost. L3 also costs money.
I would bet that the new 12" Powerbook performs very similarily to the old 12".
Early benchmarks show that the 7457 w/512k of L2 cache meets or beats the '55 clock for clock, and since L3 cache costs a lot and eats power, this is a win-win for Apple and for the customers paying less for this upgrade.
Also, it means that Apple can use the 7447, which has no tags for L3 cache and is therefore smaller, and comes in a package with fewer pins. That means on the one hand that it wasn't a drop-in replacement for its predecessor, and on the other hand that both the CPU and the board became simpler and cheaper.
FYI, L3 cache in the PowerMac G4 added about 6%-10% to CPU performance according to PowerLogix. It's not hard at all for a doubling of the much faster L2 cache to make that difference up.
Originally posted by Amorph
Actually, Mot's caching technology is very good. The L1 cache in the 7455/57 stomps all over the L1 in the 970, for instance. You get good at caching when you have to attach a ~12GB/s monster vector machine to a ~1GB/s bus.
Early benchmarks show that the 7457 w/512k of L2 cache meets or beats the '55 clock for clock, and since L3 cache costs a lot and eats power, this is a win-win for Apple and for the customers paying less for this upgrade.
Also, it means that Apple can use the 7447, which has no tags for L3 cache and is therefore smaller, and comes in a package with fewer pins. That means on the one hand that it wasn't a drop-in replacement for its predecessor, and on the other hand that both the CPU and the board became simpler and cheaper.
FYI, L3 cache in the PowerMac G4 added about 6%-10% to CPU performance according to PowerLogix. It's not hard at all for a doubling of the much faster L2 cache to make that difference up.
So, Amorph, I don't think I'm following you here. Do you mean to say that the new 'books use the 7447? Functionally, if there is no L3 in the (7457) chip, they are the same, right? But Apple says they are 7457.
Algol: clearly, someone did a cost-benefit analysis and decided they added cost of a L3 ($100? $125? I sure don't know) wasn't worth the speedup. In other words, they could actually lower the price, and increase performance a bit more than clock-per-clock, which to me is win-win. Cooler, too. Which brings up that whole battery thing.
Originally posted by machem
So, Amorph, I don't think I'm following you here. Do you mean to say that the new 'books use the 7447? Functionally, if there is no L3 in the (7457) chip, they are the same, right? But Apple says they are 7457.
There's some confusion about that. M. Isobe at Ars nabbed a Motorola document that correctly predicted the CPU clock speeds for the PowerBooks before Expo, and it listed the models as 7447s. Apple might not be distinguishing, since a 7447 is a 7457, minus the capability of supporting L3. Or there's a documentation error. It's happened before. If Apple engineering figured out that L3 was not worth it late in the game, they might have switched to the '47 after documentation had already been written, and the change just didn't get made. Who knows?
The 7447 is not exactly the same as a 7457 without L3 cache. It doesn't even have the capability to support L3 cache, so it's missing a bit of circuitry and a bunch of pins. It's physically smaller, with the benefits that implies. So once Apple had ruled out the need for L3 cache anywhere, the '47 was an obvious choice.
Algol: clearly, someone did a cost-benefit analysis and decided they added cost of a L3 ($100? $125? I sure don't know) wasn't worth the speedup. In other words, they could actually lower the price, and increase performance a bit more than clock-per-clock, which to me is win-win. Cooler, too. Which brings up that whole battery thing.
Exactly. The same amount of L3 would probably be less effective, because the L2 is more effective and the CPU will always try L2 before falling back on L3. So Apple might have been looking at a good chunk of change and power consumption along with a bigger, more expensive CPU, all for a 1%-3% performance improvement - when the better L2 cache was already providing a net gain in speed per clock relative to a 7455 with L3 cache.
Originally posted by Amorph
Exactly. The same amount of L3 would probably be less effective, because the L2 is more effective and the CPU will always try L2 before falling back on L3. So Apple might have been looking at a good chunk of change and power consumption along with a bigger, more expensive CPU, all for a 1%-3% performance improvement - when the better L2 cache was already providing a net gain in speed per clock relative to a 7455 with L3 cache.
I am not so sure of this one. I'll say that 2 MB of L3 cache would have been necessary to make a difference when the L2 cache is raised to 512 K. Intel just release the P4 EE, wich features a 2 MB L3 cache.
But's i'll guess that a 1 mb L3 cache won't make a big difference.
For the type of processor, i still believe they use the 7457. Apple never used the 744* line in his products, even if they don't used the L3 cache technology. I think they don't want to change the design of the pins connection and they want also to have options in the future. Adding some L3 cache in the future, may be an easy way to improve their computer without doing much re-engeenering.
Example, check Macconnection.com, you will see a Powerbook canned description (as if it came from Apple) still listing L3 cache.