State of DDR on g4s

wrong robot · February 4, 2003 5:46PM

I remember when the G4 towers first had DDR RAM it was a big surprise cause no one thought that the G4 mobo could support DDR RAM, then later it was discovered that it was some form of hack type deal that enabled it, first I'd like clarfication as to what that hack was? what is it about the g4 DDR RAM that makes it different from other DDR RAM.

Also is the DDR RAM on the new g4 towers the real deal? or is that never going to happen, until the g5?(970...whatever)

tht · February 4, 2003 9:02PM

The DDR hack is pretty much the exact same hack Intel had with DRDRAM (Rambus) and the PIII, and AMD had, but in reverse, with Athlons during the pre-DDR days.

The processor bus and the memory bus in all "modern" computer systems are decoupled and bridged by a core logic chip. They are not shared or necessarily synchronized at the same bus frequency. In the Power Mac G4 PC2100 DDR SDRAM systems, the DDR SDRAM has a (theoretical) bandwidth of 2100 MByte/s while the G4 CPU itself only has a bandwidth of 1067 MByte/s.

The "hack" means that all the bandwidth of DDR SDRAM is not used because it is bottlenecked at the processor bus. Apple can only wait until Moto improves the processor bus or uses a different CPU. The DDR SDRAM itself in all PowerMac systems is identical to x86 systems.

[ 02-04-2003: Message edited by: THT ]

wrong robot · February 4, 2003 11:24PM

So....x86 machines with Rambus and/or DDR ram are not running at full efficiency? or has the latest Athlon or P4 fixed this? thats really weird....so what is the maximum(theoretical) transfer speed for regular old SD ram? is that 1067? so then DDR doesn't really have any performance increase? now I'm really confused how does that work that everyone uses it?

Thanks for your response btw.

algol · February 4, 2003 11:39PM

On the new PowerMacs the DDR Ram does help performance between the System controler and the memory. However, the speed between the system controler and the CPU is not DDR. So the DDR RAM does offer a performance boost but not like it would if the bus on the G4 was also DDR.

jll · February 5, 2003 2:38AM

[quote]Originally posted by THT:

The "hack" means that all the bandwidth of DDR SDRAM is not used because it is bottlenecked at the processor bus.<hr></blockquote>

YES IT IS!!!! Ever heard of DMA? All I/O elements in the system use the remaining bandwidth.

roduk · February 5, 2003 4:05AM

As JLL says, I believe the extra bandwidth can be used by I/O components that can access the memory directly without going via the CPU. I guess it means the CPU can make full use of its (limited) bandwidth, whilst other components are making use of the remainder.

I'm not sure what I/O components use DMA, but in a non expandable computer such as the iMac (with no PCI cards), I expect the usage of the remaining bandwidth may be minimal.

[ 02-05-2003: Message edited by: RodUK ]

jll · February 5, 2003 4:53AM

[quote]Originally posted by RodUK:

I'm not sure what I/O components use DMA, but in a non expandable computer such as the iMac (with no PCI cards), I expect the usage of the remaining bandwidth may be minimal.<hr></blockquote>

Ethernet, FireWire and IDE.

tht · February 5, 2003 9:22AM

Originally posted by JLL:

YES IT IS!!!! Ever heard of DMA? All I/O elements in the system use the remaining bandwidth.

Ok, I'll amend my statement: The "hack" means that all the bandwidth of DDR SDRAM is not used by the processor because it is bottlenecked at the processor bus. Anything wrong with that?

tht · February 5, 2003 9:41AM

Originally posted by Wrong Robust:

So....x86 machines with Rambus and/or DDR ram are not running at full efficiency? or has the latest Athlon or P4 fixed this?

Back when the Pentium 3 was introduced with Rambus, Intel had many a machine with PC600/PC700/PC800/2xPC800 DRDRAM feeding a 133 MHz Pentium 3 bus. Pretty much the same bottlenecking as the DDR G4 machines. This was from about 2 to 4 years ago. The problem has since been fixed with the introduction of the Pentium 4.

AMD had the problem in reverse in that they marketed their 200/266 MHz bitrate processor bus as a performance feature while they were using PC100 and PC133 SDRAM on their machines. The processor bus had a lot of bandwidth but the memory couldn't feed it. The problem has since been fixed with the advent of DDR SDRAM.

thats really weird....so what is the maximum(theoretical) transfer speed for regular old SD ram? is that 1067?

PC100 SDRAM = 800 MByte/s

PC133 SDRAM = 1066 MByte/s

PC2100 DDR SDRAM = 2100 MByte/s

PC2700 DDR SDRAM = 2700 MByte/s

PC800 DRDRAM = 1600 Mbyte/s

2xPC800 DRDRAM = 3200 MByte/s (dual channel Rambus)

so then DDR doesn't really have any performance increase?

It does give a performance increase in processor performance. The problem is that the G4 CPUs in DDR G4 Power Macs can only accept half of the bandwidth DDR SDRAM provides. That is, the processor bus of the G4 at 133 MHz has can receive data at 1066 MByte/s while the PC2100 DDR SDRAM can send 2100 Mbyte/s.

If the G4 processor bus can receive all of the bandwidth of DDR SDRAM, then the G4 PowerMacs will have around 10 to 15% increase in CPU performance. The "hack" is just the mocking of Apple not having the CPU use all of the DDR SDRAM bandwidth. Apple has no choice but to wait to Moto to change the CPU bus or move to another processor.

jll · February 5, 2003 9:45AM

[quote]Originally posted by THT:

[qb]Originally posted by JLL:

YES IT IS!!!! Ever heard of DMA? All I/O elements in the system use the remaining bandwidth.

Ok, I'll amend my statement: The "hack" means that all the bandwidth of DDR SDRAM is not used by the processor because it is bottlenecked at the processor bus. Anything wrong with that?[/QB]<hr></blockquote>

State of DDR on g4s

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