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Posts by THT

 I'm just waiting for the inevitable other shoe to drop when Intel announces that Skylake slips to 1H 2016. I don't know if this will happen, and maybe Intel will just short-circuit's Broadwell's product life cycle, but I kind of doubt it. The current Broadwell rollout has basically been non-existent for Intel's volumes. Maybe the CEO thinks its a nice feather in their cap for saying they shipped Broadwell on time with Core M, but they have to be scrambling right now...
Find it hard to believe that Samsung and TSMC will have 14 nm and 16 nm FinFET volume in 2015. Both their 20 nm fabs were producing in volume just this Summer. It would make much more sense for them to use a refined lower power 20 nm process then go to 14/16 nm. Just too soon. Even Intel's Broadwell 14 nm rollout is going to be slow and excruciating across 2015.
 True, but I view it as more of a semantics game. A computing system has pools of memory with the smallest, but fastest pool closest to the CPU logic. The pools get bigger, but slower the further away they get from the CPU. Storage, as in HDD and SSD storage, is memory. It is a lot further away from the CPU, but is ~10 times bigger than system memory (RAM). They effect the performance a computing system as anyone who's done an upgrade from an HDD to an SSD will attest....
 Yeah. Standard fare. Intel already does this with "CrystalWell", which has been shipping for a year now. Anything Haswell with GT3e or Iris Pro graphics is a Haswell CPU/GPU with 128 MB of eDRAM on package. One is shipping in the 21.5" iMac. Intel did it with the Pentium Pro 20 years ago. Back then, L2 cache was off-package. You can upgrade your L2 cache then. With the Pentium Pro, Intel put a high speed SRAM L2 cache on the package. Time marches and lower levels of...
You definitely wind +1 Internets from me today! LOL. The DOJ and the Courts are fickle beasts. 
 Yup. Most of the CPU and GPU benchmarks are natively compiled. The web-browser tests have to pass through a HTML and Javascript interpreter, so those tests are really CPU+JIT tests.  Huh? 5.0 is 32-bit only? (I don't follow Android closely). And a 64-bit release is waiting on a 5.0.x or 5.x release in 2015? For GPU, 32-bit vs 64-bit won't make much difference. Then, with Denver, I kind of wonder what the performance will really be like with 64-bit instructions. The code...
Oh Daniel, you love to deliver blowback don't you. Michael Wolfe should be your next target! That dude is plying his Apple doomsaying stick without even a hint of knowing that he's lying. At least Hruska only is skeptical about Apple and will admit when he's wrong, sometimes. At least, I think so. He'll accept data.   It's ok to be skeptical of Apple's performance claims, but there's no excuse swallowing Nvidia's marketing spiel. They've gone through too many shame-on-me...
Those SoCs have the Cortex-A53 in them as opposed to the Cortex-A57 core. The Cortex-A53 core is simpler, lower performance, and more suitable to be fabbed on 28 nm nodes. So, it matured faster and got to market faster then the higher performance Cortex-A57 parts. The higher performance Cortex-A57 will really need a 20/22 nm fab to fit inside a smartphone or tablet TDP. The Samsung Exynos 5433, which is in the international or maybe just Korean Note 4, is supposedly a...
 Are people really confused by this? All this says is that the memory bus has 2 channels of LPDDR3 memory that are each 32 bits wide running at a clock of 800 MHz. Math: 2 channels x 32 bits per channel x 800 million cycles per second x 2 32-bit transfers per cycle (DDR) = 12.8 GB/s of theoretical memory bandwidth. It's says nothing about the CPU ISA and instruction size. The memory bus width sizes can vary quite a bit. Apple shipped SoCs with 128 bit memory buses in the...
 Yeah. Everything is a tradeoff. They'll go to 2 GB sooner or later. But it seems today they believe negatives in user experience with 1 GB are better than the negatives with 2 GB.
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