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Posts by smalM

The test sites show a sort of "best case" for USB as there is normaly only one EHCI controller implemented which all USB2 connections have to share.Intel commited to build FW800 into their future chip sets only a week or two before Apple announced the CPU switch. Coincidentally
PCIe ATI 9650? Where did you find that? ATI AGP cards are 9nnn. The PCIe cards are Xnnn or X1nnn. Only the X8nn got the Rialto bridge chip. BTW a X1300 would be much better than the 9200 the mac mini has now, even the new ones with 64MB on a 128bit bus.
In fact they do not sell the developer kit
I hate Merom - it makes me think about buying a notebook instead of a desktop
This is not CPU bound. The system controllers in pre G5 systems can't access more than 2 GB RAM.
I assume the memory controller cannot handle the 4 DIMMs at the higher speed. In PCs the memory controller can often handle 2 DIMMs at a lower speed and only 1 at higher speed. Or has to use registered DIMMs instead. (Of course this is always number of DIMMs per memory bank).
GMA900 is both, more and less sophisticated than the ATI 9200 as it has 4 pixel pipelines at directX9 level but lacks any vertex shader hardware (CPU has to do all the setup). That's ATI 7000 level....
Intel stated at the last idf that Yonah will coexist to Merom till Meroms transition to 45nm process in 2007.
Could you explain that "each directions' traffic is 1/4 speed"?
Yes I know the difference between data rate and bus clock. "bi-directional bus"? The bus is dual unidirectional! One way is 1/4 CPU (=clock of the memory controller) *2 (double pumped bus) *4 (32bit width bus) *8/9 (packeging overhead) = 4.4 GB/s bandwidth in each direction for the 2.5GHz PM. Hope that makes it clear for you what I mean. Sorry, english was only my third foreign language in school....
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