or Connect
New Posts  All Forums:

Posts by smalM

This is not CPU bound. The system controllers in pre G5 systems can't access more than 2 GB RAM.
I assume the memory controller cannot handle the 4 DIMMs at the higher speed. In PCs the memory controller can often handle 2 DIMMs at a lower speed and only 1 at higher speed. Or has to use registered DIMMs instead. (Of course this is always number of DIMMs per memory bank).
GMA900 is both, more and less sophisticated than the ATI 9200 as it has 4 pixel pipelines at directX9 level but lacks any vertex shader hardware (CPU has to do all the setup). That's ATI 7000 level....
Intel stated at the last idf that Yonah will coexist to Merom till Meroms transition to 45nm process in 2007.
Could you explain that "each directions' traffic is 1/4 speed"?
Yes I know the difference between data rate and bus clock. "bi-directional bus"? The bus is dual unidirectional! One way is 1/4 CPU (=clock of the memory controller) *2 (double pumped bus) *4 (32bit width bus) *8/9 (packeging overhead) = 4.4 GB/s bandwidth in each direction for the 2.5GHz PM. Hope that makes it clear for you what I mean. Sorry, english was only my third foreign language in school....
No! The ratio CPU to memory controller is 4:1. What you mean is the ratio CPU to bus data rate which is 1:2 as the bus is DDR. And bandwidth on the bus is raw transfer rate minus overhead for the packeges. IBM claimed 8:9 for throughput:raw transfer rate.
The ratio CPU/Memory-Controller Apple uses is 4 for the PM and 6 for the iMac. We don't know the ratios the 970MP can use but the 970FX can use 1, 2, 3, 4 and 6. A ratio of 3 already means a memory controller running at 833 MHz, ca. 5900 MB/s bandwidth in each direction and perhaps the need of watercooling for the controller
Just the same level as your rant
It would be a PAL or SECAM tuner for Europe
New Posts  All Forums: