[quote]Originally posted by Outsider:
<strong>What of UMA3? Wasn't this supposed to be the DDR/PCI-X platform we all waited for in the pre-AI blackout? It seems kind of antiquated now. The new paradigm in chipsets is integration! And the roadmap is all different now. In the past it was straight foward: you would have a processor that connected to a PCI/memory controlled dubbed 'northbridge' which in turn connected to the PCI bus, memory (RAM), and peripheral controller (aka southbridge). Now it's a bit complicated; we have a CPU connecting to a system controller that may or may not be PCI 32/64, and the CPU has a direct connection to RAM and on top of that the North and southbridge seem to have combined and, and.... man is this complicated. And now we have a RapidIO and HyperTransport conflict. What will Apple use and how? Maybe they will use both. What direction do you think Apple is heading towards?</strong><hr></blockquote>
Regarding RapidIO and HyperTransport, I'm virtually certain that they'll use both. See <a href="http://forums.appleinsider.com/cgi-bin/ultimatebb.cgi?ubb=get_topic&f=1&t=000010
" target="_blank">this thread</a> for why. I'm also confident that it will use DDR memory. Among other reasons, Rambus is a proprietary, single-company, product. I think with Apple's well publicized parts shortages for some of their high-end products, they won't go that route again. As for PCI-X, is the spec for that even finalized yet? If so, I expect to see it. If not, I hope that they'll upgrade the current slots from 33MHz to 66MHz. I would also like to see eight interleaved memory slots. I don't know the technical details of doing this, but I know that if they did the same way I would, it would give up to 8x the memory bandwidth (depending on how many slots are filled and how much data you manipulate at a time) without really affecting the latency. Did I leave anything out?