[quote]Originally posted by DigitalMonkeyBoy:
<strong>I remember a while back that there was a lot of talk about "DDR-133" and "DDR-266" being planned for UMA2.
What happened? Will we see DDR 266 on the G5-based motherboard?
Any news of raising the bus speeds?
</a> claims 400 MHz as a possibility.
Whilst a 400 MHz traditional front side bus is possible, there is nothing in Motorola´s docs that show they have one. Using a 400 MHz bus with 266 MHz RAM doesn´t make all that much sense. However I see two possibilities, RapidIO or Hypertransport, Motorola have RapidIO for their comms chips, but Apple are members of the Hypertransport consortium. My reasoning is:
The valid information we have from Motorola show an upcoming embedded G5 class chip with an embedded DDR memory controller, the G5 will have an enormous number of pins (about 550 IIRC) and a ridiculous number of logic transistors, which all leads me to believe the G5 will have a separate memory bus and "front side bus". The memory bus will probably a single channel (64 bit) DDR 266 or possibly DDR 333, a dual channel system would be possible but might result in an expensive motherboard and the necessity to add memory DIMMS in matched pairs although a dual channel DDR 333 system would yield 5.4GB/s bandwidth putting even the Pentium4 in the shade. Given a separate memory bus, the front side bus will probably be a hypertransport (400MHz double pumped 16 bit = 1.6GB/s or 32 bit = 3.2GB/s but that would require almost 200 pins by itself) bus, communicating with an AGP bridge and a more-or-less conventional south bridge.
The problem with a RapidIO bus as a front side bus is that a single pumped 16 bit 400MHz bus would only have 0.8GB/s bandwidth, the same as PC100 memory, which would be just enough to power a 4xAGP and an ordinary PCI bus, but would kill any multiprocessor hopes.