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Originally Posted by wizard69 
You might want to read the Flash 101 here: http://www.eetimes.com/design/memory...-to-NAND-flash. If you do I can't see how one could possibly call NAND Flash Random Access Memory. You can't even do a random access cycle randomly.

You might want to read the Flash 101 here: http://www.eetimes.com/design/memory...-to-NAND-flash. If you do I can't see how one could possibly call NAND Flash Random Access Memory. You can't even do a random access cycle randomly.
Geez.. The article repeatedly references the random accesses and doesn't contradict essentially constant access time for any byte in the array. Arguments that try to use burst reads byte sequences are improperly using read optimizations, because it is random fist byte access that determines the constant access time, not sequential accesses. All forms of RAM implement some type of burst read and/or write for the sequentially accessed bytes.
So , no nothing new in that article and it does not support you position that NAND Flash is not random access. I'll agree with the article that NAND Flash is not suited for "direct random access", but what the author is talking about is getting at a single byte off the page, especially if you need to change it. You can always get there in roughly constant time, and it will always take roughly constant time to replace the byte, but you have to so a shitpot of extra overhead work that doesn't help the actual task you are trying to accomplish. But it's still essentially constant access time to the first byte, so still RAM, even if it isn't smart to use it naively that way.
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Still incorrect, even by your reference and it reads well.
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NOR is a red herring, its RAM too. But yes NAND was specifically designed as a secondary storage technology.
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Not at all. I am simply saying RAM is nearly constant access time to any random byte in the storage array. If you are referring to my main buss comments, sickle cycle can depend on the specific bus you put it on, but single cycle is a red herring because the RAM just means essentially constant access time to the first byte. The sub-nanoscecond propagation through the storage array transistors and differing trace lengths from different physical positions on the array make for those differences that fall in the "essentially constant" term. There is no perfectly constant access in the physical world at an arbitrary resolution. But at the package level, and the discrete time intervals the bits are clocked off, it will be constant. I just went a little deeper into the description to cut off the ridiculous arguments about the inconstancies and where they actually come from. Not that you would have gone there, but there are some on the boards that do and a preemptive word just keeps the thread shorter.
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That's a personal convenience, not a technical definition. Technically we can access any byte anywhere in the machine's storage, that's the whole idea of having an address space. And the address space cares not what it is implemented on.
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Main memory is main memory, or also called primary memory/storage. The specific technology that you implement a main/primary is inconsequential to it's position in the architecture. What will we call a memristor primary memory, especially if it is not constant access to every byte in the array? But still more than a million times faster than todays flavors of multi-transistor RAM? THAT'S why it is important to not confuse a technology attribute name with it's architectural use. When the implementation tech fundamentally changes your incorrect terminology forces you to compare them as old and new architectures, which aren't really old and new at all, but the same architecture, just with new components. It's drastically simpler to discuss the effect on correctness and performance when it is just comparing different black boxes in the same system.
And OBTW University of Minnesota, it was a top 10 in CS then, but a lot of retirements happened in the intervening years. Still not a slouch of a school.
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Originally Posted by wizard69 
BS! Main memory is the computers primary memory that CPU or memory manager directly addresses when executing programs or accessing data. It can be DRAM or SRAM if you want timely read write access. It can also be NOR flash if writing to that storage isn't required. Beyond that there are other new technologies that allow for non volatile read write access. NAND flash isn't one of these, the normal way to use NAND is to load RAM with data from the NAND flash much like a disk access.

BS! Main memory is the computers primary memory that CPU or memory manager directly addresses when executing programs or accessing data. It can be DRAM or SRAM if you want timely read write access. It can also be NOR flash if writing to that storage isn't required. Beyond that there are other new technologies that allow for non volatile read write access. NAND flash isn't one of these, the normal way to use NAND is to load RAM with data from the NAND flash much like a disk access.
I don't know what you are arguing here other than NAND flash isn't efficient to use as a primary memory. I'll agree with that as I already did in the second paragraph. As for the rest you are simply agreeing with my above paragraph that the implementation is NOT the architecture. You really need to pay attention to your own thoughts because now you are making my points for me, which is actually a good thing all around.
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Yes. Now if you can read your own previous paragraph and see that you have been blind to the fact you actually agree with me but initially used the sloppy terminology we can all get on with doing good work.
Hiro's Hall of Shame ignore list: Tulkas -- because we know he wasn't born dumb.
Hiro's Hall of Shame ignore list: Tulkas -- because we know he wasn't born dumb.





