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The G5 and what it means for future Macs - Page 4

post #121 of 357
[quote]Originally posted by SteveS:
<strong>

I understand what you're saying, but it's really still a bit premature to worry about clock speed before we know anything substantial about the G5 design. For example, if the rumored SPEC performance (as reported by the Register), is correct or even ball park (which I'd be surprised if it was), it would take a 4 GHZ P4 to even start to approach a 1.6 GHZ G5. That said, worrying about MHZ at this stage is sort of like worrying about how many RPMs your next car will do before you've even decided to stick with the old 4cyl. engine or go with a new 8 cyl. engine. MHZ (like RPM) is a very relative measure of performance.

Steve</strong><hr></blockquote>

RPM fits in but you must add the torque factor. The 125 cc KTM can run up to 14,000 rpm with 60 HP and the KTM 500 has 50 HP but the 125 will never catch the 500 pulling up a hill.
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post #122 of 357
[quote]Originally posted by HOS:
<strong>

Don't forget that RIO is a switched bus- this means that any two (unique!) given devices can talk together with full theoretical bandwidth between them. So, for example, if the HDD needs to write to RAM, there's (in this 500 MHz 16-bit RIO example) 2 GB/s for it to do so, while at the same time, there's 2 GB/s for (say) two CPUs to talk to each other.

Think switch instead of hub, to borrow a networking analogy.

As for future scaling, although I could be wrong, I really don't see this as a problem for RIO. One of the benefits of reducing pin count by moving to a "narrower" bus (16 bits for RIO instead of 64 for current system busses, a la 60x or MPX) is that it makes it easier to design circuits for reduced crosstalk, leakage, etc.

Although if I wanted to complain, I would argue that Apple's chipsets are Apple's problems, and Apple needs to spend more of that $4x10^9 kitty on designers.

A valid question is, since the PMG4 is supposed to Apple's high-end "workstation-class" computer, why is it only using a 64-bit bus? MPX allows for 128. Also, why hasn't, say, a 128-bit bus between northbridge and CPU been implemented, and dual 64-bit busses out to RAM (from the northbridge) been implemented to effectively interleave?

In other words, a lot of Apple's performance problems can be laid squarely at the feet of Apple instead of Moto.
</strong><hr></blockquote>

Apple's $4 billion is needed to supplement their income so they remain profitable. It's also going to cover them through weak quarters, like I expect the next couple to be.

As somebody else supplied: the MPX's theoretical 128-bit width isn't supported by any shipping part.

The RapidIO bus is point to point, but if everybody wants to talk to one point (i.e. the CPU/memory controller/memory) then they all have to share bandwidth. And the 2 GB/sec throughput is theoretical, realized throughput is considerably lower due to packet overhead. Small transactions have a disproportionaly large effect on throughput (i.e. somebody sending 1 byte is almost as expensive as somebody sending 10 bytes).
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post #123 of 357
[quote]Originally posted by SteveS:
<strong>

I wouldn't worry about the validity of this screen shot. If by some odd chance you think this might be real (http://homepage.ntlworld.com/phillip.briggs1/G5_3.htm), I suggest you check out the other pages on this web site that were not part of the original link:

<a href="http://homepage.ntlworld.com/phillip.briggs1/G5_1.htm" target="_blank">http://homepage.ntlworld.com/phillip.briggs1/G5_1.htm</a>
<a href="http://homepage.ntlworld.com/phillip.briggs1/G5_2.htm" target="_blank">http://homepage.ntlworld.com/phillip.briggs1/G5_2.htm</a></strong><hr></blockquote>

Yeah, I saw those "iMac G5s" earlier...just didn't realize the ASP shot was from the same poster.. <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />
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post #124 of 357
You should have realized immediately that it was fake...the carbon ASP (not the one in the term) displays the MHz rounded up, I.E. a 866.66666 on to infinity G5 would appear as 867MHz. Besides you know it's crap anyway .
post #125 of 357
Well, now that both Dorsal and Kormac have come out of the woodwork, I suppose I should weigh in with my questions as well.

Dorsal, do you note any other capabilities on these machines other than "under-the-hood" improvements (e.g. introduction of new technologies like firewire)? Is there any significant chip-based performance boost (e.g. more altivec units). Or is what you are saying that these things are essentially being built to just do a lot faster what the existing machines already do.

Kormac, good to see you back. I for one noted the intro of the 23 inch display. What are you implying about what might come next? Those links were to pretty boring technologies, not to anything that seemed Apple-like.

Hope springs eternal,

Mandricard
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post #126 of 357
IBL!
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IBL!
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post #127 of 357
[quote]Originally posted by Matsu:
<strong> </strong><hr></blockquote>

Check your blood pressure Matsu, you're gonna pop a vein.
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post #128 of 357
[quote]Originally posted by Programmer:
<strong> I think the point of my original message was missed</strong><hr></blockquote>

Point taken <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />

[quote]Originally posted by Dorsal M:
<strong> The processor speed is based on a ratio of the RapidIO bus; in this case 500MHz * 3, or 1.5GHz. The minimum ratio is 2:1 therefore on a 500MHz system bus you will at the minimum acheive 1.0GHz. </strong><hr></blockquote>

Where did you get that from, I must have missed something in the white papers <img src="confused.gif" border="0">
post #129 of 357
[quote]Originally posted by DOSAL:
<strong>I just got through with the G5 and this machine rocks. Unfortunately, there are a lot of bugs and one of my superiors just said to leave the machine and redesign a new chip. One of the main problems is that the DDR 133 doesn't support the keyboard and so the drivebay won't open because of a glitch in the airport card that links the case to the hard drive of the flash card of the BRAND NEW 23" CINEMA DISPLAY. Another bug is that the chip stops working after a couple of controlled power surges (I don't know why). Then the mobo, um, breaks and, um, won't work. So Apple really needs to finish the work on this machine, um, But it really rocks!!!</strong><hr></blockquote>

Funniest thing I've read in long time. I nearly pissed in my pants laughing so hard!!

<img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
post #130 of 357
[quote]Originally posted by kormac77:
<strong>

23" Wide UXGA LM230W1

What will be next ?

<a href="http://www.lgphilips-lcd.com:8888/English/news/n_cozy.html?idx=401&offset=0&pkinds=movement&pname =news" target="_blank"> LG Philips LCD</a>

or

<a href="http://www.samsungelectronics.com/semiconductors/TFT_LCD/product_news/semiadmin_1010104542921_108.html" target="_blank">Samsung LCD</a>

And if you can remember what I was talked about, I think we will see good sign soon.

P.S.: SAMSUNG & LG.Philips LCD Co., Ltd is making TFT-LCD for New iMac.

[ 03-21-2002: Message edited by: kormac77 ]</strong><hr></blockquote>

The only interesting thing about the first link is the 17" PCTV (something that I have always thought that an iMac configuration should has to satisfy consumers w/o a lot of space such a the college market) implying that maybe when the iMac goes 17" that this will be available? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />

The second article also implies this. But look at this excerpt:

"Many LCD TVs currently on the market still require some technological advancement; for example, their slow pixel response time causes a √Ęghosting√Ę? problem. However, Samsung Electronics has accomplished some technological breakthroughs."

Now I don't know what this means for the LCD display on a PC... nothing in this article besides that Samsung can make REALLY BIG (40") LCD displays... :confused:

[edit: shortened links in quoted text - Amorph]

[ 03-27-2002: Message edited by: Amorph ]</p>
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post #131 of 357
[quote]Originally posted by smalM:
<strong>Where did you get that from, I must have missed something in the white papers :confused: </strong><hr></blockquote>

It wouldn't be a function of the RapidIO spec, it would be a function of the RapidIO implementation on the processor. If he is who he claims then he could well have access to that sort of processor documentation. It could also be a poor assumption. Or he could be making all this up just to toy with us.
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post #132 of 357
[quote]The RapidIO bus is point to point, but if everybody wants to talk to one point (i.e. the CPU/memory controller/memory) then they all have to share bandwidth. <hr></blockquote>
--Programmer

Yup- point-to-point is why I threw in the "unique!" (implying not shared) line in my post. Sorry it wasn't sufficiently clear.

Anyway, as per the older supposition, the assumption about the G5 is that it will adopt a built-in DDR controller, and thus move from a traditional shared bus approach (as in your CPU/memory controller/memory example above) to one where a CPU's local memory is on a "backside bus", to adopt an older expression.

Thus, in a multiple-CPU situation, each CPU gets its own local memory. However, in order for CPU 1 to access CPU 2's local memory, you use the RapidIO bus to do so.

Pardon the ASCII art:

local DDR RAM &lt;--&gt; CPU 1 &lt;--&gt; RIO bus &lt;--&gt; CPU 2 &lt;--&gt; local DDR RAM

Further, the RIO bus then also provides a way to get to shared subsystems like hard drives, PCI, etc. Again, since this is a switched bus, CPU1 can (say) talk to the hard drive while CPU2 is talking to the AGP card.

It gets really interesting because this approach then assumes you'll need a really big address space- making the jump to 64 bits necessary. Especially as the number of CPUs scale up, assuming 2-3 GB per CPU means we'll get past the 4 GB limit of 2^32 very quickly.

Pretty neat, huh?

-HOS
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post #133 of 357
Hmmm... I don't think a large address space is implied. The physical addresses that the G4 can generate are probably sufficient (36 bits, I think?).
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post #134 of 357
[quote]Originally posted by THT:
[QB
What is really confusing me is that Apple is a member, a founding member, of the HyperTransport Consortium. Why invest the resources when your processor vendor is the main force behind a competing bus architecture, and will use RapidIO in its future processors? Unless Apple convinced Moto to design a PPC processor with a HyperTransport bus, why promote it? And using HT to connect core logic chips seems a waste when RIO is perfectly fine for it.[/QB]<hr></blockquote>

My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version .

More likely scenario, Apple paid the $40,000 or whatever it costs now to be premier member in the HT consortium for a device/purpose not yet apparent or just for the media exposure. Since Motorola would of course want Apple to use their RapidIO technology I can't imagine them designing the G5 to work with HT.
post #135 of 357
From Eskimo:
[quote] My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version. <hr></blockquote>

You call that a wild ass theory? Pah! I fart in the general direction of your wild ass theory!

OK, here's mine: Apple have a skunkworks project to combine AMD's processors with a PPC-oriented software morphing layer based on Transmeta's technology.

I like this game. Just look up the members of the <a href="http://www.hypertransport.org/organisation" target="_blank">hypertransport consortium</a>, and conjure up ways that they can combine forces to lead Apple in triumph against the forces of darkness. Do try this at home, kids!
post #136 of 357
well shit, while we're on wild ass theories, here's mine.

Nvidia is now bored after conquering the GFX market, so they're looking around for some asses to kick.

they've started on chipsets to get their feet wet, and although they aren't at the top yet, they fully expect to hand VIA their collective asses and dominate the chipset market.

so what's next? they decided that Apple is a nice little company that needs a hand, so they decide to make computer processors to go hand in hand with their chipsets and GFX chips. apple's next series of chips will come from Nvidia, and apple will once again be a viable competitor.
post #137 of 357
[quote]Originally posted by Eskimo:
<strong>

My wild ass conspiracy theory is that Apple intends to leverage Nvidia to make a version of their next integrated core chipset for Apple's machines. Nvidia already uses HyperTransport with AMD's EV6 bus on Nforce motherboards and Intel's GTL+ bus inside the Xbox. Why not go for the triple crown and make a MPX compatible version .

More likely scenario, Apple paid the $40,000 or whatever it costs now to be premier member in the HT consortium for a device/purpose not yet apparent or just for the media exposure. Since Motorola would of course want Apple to use their RapidIO technology I can't imagine them designing the G5 to work with HT.</strong><hr></blockquote>

Here is my guess: There are so many new standards out there right now, and it is hard to guess which one will come out on top, Apple is just positioning itself so that whichever one catches on they will be right there. I think that Apple simply doesn't want to get caught in the wrong seat at the end of the song.

Thinking more about it, it would seem that each have there strengths and weaknesses. A daughter card with CPU, Ram, and AGP would be nice. HyperTransport would make the wiring easier, and ensure that the system works well with Nvidia cards. But how about a daughter card that would allow the PCU and Video board to share memory?? I think that Apple really likes the idea of one controller chip, like in the hypertransport protocol.

Ty
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post #138 of 357
[quote]Originally posted by Dorsal M:
<strong>Work on the G5 (MPC7500) is progressing nicely at Motorola ...</strong><hr></blockquote>

Very nice.

However, this sure sounds like a rather conservative design.
  • 133 MHz DDR (I really want to be able to go up to 266 MHz [533 MHz equivalent], or, at least, 128 bit) is on the low side (however, as with Motorola's 8500, the memory controller was put on-chip to facilitate rapid increases in memory speed as processor speeds increase).
  • 500 MHz RapidIO is half the speed RapidIO has been capable of for about a year now.
post #139 of 357
No, no, no, no.

Graphic chips are too far from the CPU currently, and a higher bandwidth connection is required. The level of integration will always increase, and the speed of interconnects will always improve. The graphics engines include advanced memory controllers, so an obvious direction for the graphics companies to move is into the chipset space. If they don't the chipset companies will move into the graphics space and do a louzy job of it. The problem is that the memory controllers are moving onto the CPUs, and the chipsets are being replaced by interconnect strategies like RapidIO. So what is going to happen to the graphics chips? They need to cozy up to the CPU, which means either moving onto the CPU or using a dedicated highspeed interconnect to the CPU's onchip memory controller. Sharing the system interconnect with the rest of the system is insufficient for the graphics engine's ravenous appetite for bandwidth.

Eventually I expect to see processors with onchip memory controllers and 2 bus interfaces -- one to the graphics engine, and one to the rest of the system. The graphics engine may reside on the CPUs chip in highly integrated cases, but for a while (i.e. a few years) they will just be connected by the fastest available point-to-point mechanism. nVidia likes HyperTransport, and I think ATI might jump on that bandwagon too (if they haven't already). Since these buses are designed to be simple and easy to implement, it wouldn't surprise me to see both a RapidIO and a HyperTransport port on future PowerPCs.

The 8540 documentation on the Motorola site talks about a modular approach to designing processors, with customer designed sections. The G5 that Apple eventually uses is likely to follow the same philosophy, even if it is otherwise different than the 8540. This could allow Apple to add a HyperTransport interface for a high speed graphics system, in addition to the standard RapidIO bus that handles all the other interactions with the system.
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post #140 of 357
"Work on the G5 (MPC7500) is progressing nicely at Motorola and I can only assume Apple had a role in the development as there are many features included that are condusive to a top-notch desktop processor capable of bring the PowerMac into the 21st centure as a real performer in the compute intensive field."

I hope you're right masked man.

<img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />

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post #141 of 357
one definatly good thing about dorsal posts is that they bring the community together a bit with "inside" info that is posted in a very believable manner, to allow for some good interesting ideas and threads to form.

whether or not dorsal is actually telling leaked info, or if he is just a really good writer with a keen imagination, he's posts usually invoke a strong discussion and out of the discussion good ideas and predictions usually stem
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post #142 of 357
Thread Starter 
An undisclosed amount of time ago we received 2 new PowerMacs for testing. These were in generic G4 cases but were painted another color (black). I doubt this is indicative of future case but an attempt to obfuscate what the real case will look like.

These 2 systems are similar to the last one we received. Both are G5 based running at speeds of 1.33GHz and 1.66GHz. As you can tell from these speeds, the RapidIO bus has been upgraded from 500MHz to 667MHz, most likely, in my opinion, to be more syncronous with a DDR-333 RAM option, although this is not as necessary as those to busses are not shared as they were with MPX. I beleive this processor also is limited to processing 32bit integers but memory addressing has been increased to the 40-48bit area. In the documentation it shows the motherboards having support for 64GB but that processor can access more in future motherboard implementations. Possibly as high as 4TB (42bit addressing). The heatsinks are minimal with no active cooling so higher speed processors are likely down the pipeline. These units have full support for PC2700 DDR-SDRAM and contain 3 slots on the card. AGP remains 4X (GeForce4 MX) and the standard 4 PCI slots are all operational. Testing will begin sometime today. I hope to have more details soon.
post #143 of 357
[quote]Originally posted by Dorsal M:
<strong>An undisclosed amount of time ago we received 2 new PowerMacs for testing. These were in generic G4 cases but were painted another color (black). I doubt this is indicative of future case but an attempt to obfuscate what the real case will look like.

These 2 systems are similar to the last one we received. Both are G5 based running at speeds of 1.33GHz and 1.66GHz. As you can tell from these speeds, the RapidIO bus has been upgraded from 500MHz to 667MHz, most likely, in my opinion, to be more syncronous with a DDR-333 RAM option, although this is not as necessary as those to busses are not shared as they were with MPX. I beleive this processor also is limited to processing 32bit integers but memory addressing has been increased to the 40-48bit area. In the documentation it shows the motherboards having support for 64GB but that processor can access more in future motherboard implementations. Possibly as high as 4TB (42bit addressing). The heatsinks are minimal with no active cooling so higher speed processors are likely down the pipeline. These units have full support for PC2700 DDR-SDRAM and contain 3 slots on the card. AGP remains 4X (GeForce4 MX) and the standard 4 PCI slots are all operational. Testing will begin sometime today. I hope to have more details soon.</strong><hr></blockquote>
perhaps we will see this machines in junuary, MWSF seems to close for the release of this machines wich seems to be still in beta developpement.
post #144 of 357
[quote]Originally posted by Dorsal M:
<strong>These 2 systems are similar to the last one we received. Both are G5 based running at speeds of 1.33GHz and 1.66GHz. As you can tell from these speeds, the RapidIO bus has been upgraded from 500MHz to 667MHz, most likely, in my opinion, to be more syncronous with a DDR-333 RAM option, although this is not as necessary as those to busses are not shared as they were with MPX. I beleive this processor also is limited to processing 32bit integers but memory addressing has been increased to the 40-48bit area.</strong><hr></blockquote>

It seems a bit odd to me that a "G5" based system would be limited to 32bit integers. For starters, how would you know? Do you have updated, 64bit compilers? As a programmer, my only way of testing would be to do a sizeof(int) in C. What method are you using?

Also, I don't mean to sound like a skeptic, but how about a few performance benchmarks in addition to the specs. It would seem to me that you are already breaking a NDA already just by discussing the specs, assuming one exists. So, let's see some performance benchmarks, please!

Thanks!

Steve
post #145 of 357
Okay, I'm no expert.

But isn't the first iteration of the G5 32 bit?

Won't the altivec still be able to issue higher than 32 bit instructions?

I'm dreaming of this spec come July.

I pray to Big G that Dorsal is right. Sounds like a scorcher...

I'm not bothered about spec marks. But could you give a 'perceptual' indication of performance on things like Photoshop or MORE importantly 3D app eg Lightwave, Maya, Cinema 4D framerates in Quack III? Does it seem twice as fast? How does it compare to PC boxes you've seen eg Pentium/Athlon?

Does it hang in FPU performance? An area the Athlon is strong on but the G4 is weaker on...

Come to think of it.

What is the G5 influence/factor on altivec? Does it drive altivec 'mini superchip on a chip' faster?

Who's making it. Motorola? Or IBM?

I just hope apple delivers.

If they don't, I wait until 2003. I've waited four year for my next Mac. I can wait a bit longer for 'the best'.

By your previous experience of receiving 'seed' machines...will this one be about ready for Seybold this year?

If not, what's holding up? Apple politics, Moto' yield problems? Motherboard issues? Or merely routine software /'x' on G5 testing issues...for incompatibility issues?

Another question...dual boxes? Do they roar like lions? Or squawk like Mcaws?



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post #146 of 357
[quote]Originally posted by SteveS:
<strong>
It seems a bit odd to me that a "G5" based system would be limited to 32bit integers. For starters, how would you know? Do you have updated, 64bit compilers? As a programmer, my only way of testing would be to do a sizeof(int) in C. What method are you using?
</strong><hr></blockquote>

sizeof(void*) would be a better test. On some 64-bit machines the type "int" (and even "long int") remains at 32-bits, with "long long int" used to get a 64-bit value.

This is probably the most disappointing DorsalM message I've seen -- it just doesn't sound very technically savvy. How does he know its a G5? Is this the Apple machine designation or the Motorola chip designation? Or just his supposition? The information about the physical addressing capabilities is a little odd...
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post #147 of 357
If this is true, then the future of the Macintosh platform seems much, much brighter than predicted by some in some of the other active threads.

Can anyone who has tested PowerMacs, especially the first G4's, in the past under NDA describe the the state of the machines at certain intervals before the machine's release. This may give us a clue as to how long we have to wait for the DorsalMac G5. I would think that disclosure of this information would be perfectly legal as the NDA's would have long since expired.
post #148 of 357
Yes, However Dorsal ahs consistently been waaayyy early w/ his info. He gave the specs for the 1ghz/133 bus PMG4s long before they were released. He then had sweeter prototypes (or claimed to) before those G4s came out. Look back to the previous generation of prototypes (pre-G5) to get a better idea of what we might see come MWNY.

Dorsal's info has been surprisingly accurate, but we always expect to see the macs he talks about a good four-six months early.

I'd put these G5s at about Sept-November 2002, earliest.

I'd guess we'll get 1.4ghz G4/266mhz bus, rapid io, and raycer implementations this summer.
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post #149 of 357
[quote]Originally posted by stimuli:
<strong>
Dorsal's info has been surprisingly accurate, but we always expect to see the macs he talks about a good four-six months early.
</strong><hr></blockquote>

As Dorsal's first post in this topic was almost exactly 4 months before MWNY 2002, shouldn't you be concluding that them being announced at MWNY is at least quite probable?
post #150 of 357
[quote]Originally posted by Programmer:
<strong>

sizeof(void*) would be a better test. On some 64-bit machines the type "int" (and even "long int") remains at 32-bits, with "long long int" used to get a 64-bit value.

This is probably the most disappointing DorsalM message I've seen -- it just doesn't sound very technically savvy. How does he know its a G5? Is this the Apple machine designation or the Motorola chip designation? Or just his supposition? The information about the physical addressing capabilities is a little odd...</strong><hr></blockquote>

Regarding the "sizeof()" this is why I specifically asked if he was using a new compiler. The chip being able to handle 64bit INTs is one thing, the compiler recogizing it is another. Yes, I would certainly check shorts, ints and longs. Still, this would only tell me if the compiler is able to recognize the 64bit hardware. I chose INTs for my example because the commonly accepted definition of a "64bit" chip is one which can has (at least) a 64bit address space and one which can natively handle 64bit INTs.

As for these Dorsal posts, I'm more than skeptical. My point is this, why go into details about the hardware, yet not even discuss the performance, other than in some vague sense. Even if he's full of BS, he could at least give us some BS benchmarks! <img src="graemlins/smokin.gif" border="0" alt="[Chilling]" /> Afterall, the point of all these rumors is entertainment, right? Along that line, I'd like to hear what his method of determining the INT size was.

Steve
post #151 of 357
[quote]Originally posted by SteveS:
<strong>

As for these Dorsal posts, I'm more than skeptical. My point is this, why go into details about the hardware, yet not even discuss the performance, other than in some vague sense. Even if he's full of BS, he could at least give us some BS benchmarks!

Steve</strong><hr></blockquote>

I was wondering that too but then I thought if you were testing these machines speed isn't what you're looking for necessarily. It's stability, compatibility etc etc.I doubt these people can stick Q3Arena on it and frag its guts out
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post #152 of 357
"Even if he's full of BS, he could at least give us some BS benchmarks!"




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post #153 of 357
Question:

On a 32 bit proccessor, the assembly registers are EAX, EBX, EDX, etc. Those are the 32 bit registers. Now what are the 64 bit registers called?

I am taking an assembly class this semester (386 yuk), so it is all 16 bit stuff we are learning, but I was just wondering what the new registers would be accessed as.
post #154 of 357
[quote]Originally posted by kupan787:
<strong>Question:

On a 32 bit proccessor, the assembly registers are EAX, EBX, EDX, etc. Those are the 32 bit registers. Now what are the 64 bit registers called?

I am taking an assembly class this semester (386 yuk), so it is all 16 bit stuff we are learning, but I was just wondering what the new registers would be accessed as.</strong><hr></blockquote>

Your question only applies to AMD's x86-64 architecture as both Intel and Motorla are not using anything resembling x86 as their 64bit solutions, and you are only learning assembly for x86. x86-64 would rename EAX, EBX, EDX, etc. to RAX, RBX, RDX, etc. See diagram below.

post #155 of 357
The PowerPC registers are called R0-R31 for the integer registers, FR0-FR31 for the floating point unit, and VR0-VR31 for the vector unit. Or something like that. In a 64-bit implementation the R0-R31 registers just get bigger.


Its about time somebody adds more registers to the Intel instruction set... its just rather funny that its AMD!!
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post #156 of 357
x86 processors really have a lot more registers than that, they are just not programmer accessible. Those shadow registers are used transparently (there can be some hinting from the compiler) and actually turn out to work quite well.

More bothersome is the format of the x86 operation format (a op b -&gt; a) vs the PPC (a op b op c - &gt; d). That really screws up the register situation.
post #157 of 357
[quote]Originally posted by *l++:
<strong>x86 processors really have a lot more registers than that, they are just not programmer accessible. Those shadow registers are used transparently (there can be some hinting from the compiler) and actually turn out to work quite well.

More bothersome is the format of the x86 operation format (a op b -&gt; a) vs the PPC (a op b op c - &gt; d). That really screws up the register situation.</strong><hr></blockquote>

Yeah, the shadow registers help a lot, but it would be a lot more straightforward if they didn't have to. The x86 gets a lot more use out of its L1 cache as a result.

The other thing that would help the x86 would be making the setting of the CCR optional on a per-instruction basis. I've seen some very smart things done by compilers, allowing branch folding to happen.
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post #158 of 357
[quote]Originally posted by Programmer:
<strong>
The other thing that would help the x86 would be making the setting of the CCR optional on a per-instruction basis. I've seen some very smart things done by compilers, allowing branch folding to happen.</strong><hr></blockquote>

Yeah, I've always longed for some Creedence Clearwater Revival on a per-instruction basis.
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post #159 of 357
[quote]x86-64 would rename EAX, EBX, EDX, etc. to RAX, RBX, RDX, etc.<hr></blockquote>

You can also use r0-r7, right?
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post #160 of 357
[quote]Originally posted by Mac The Fork:
<strong>

You can also use r0-r7, right?</strong><hr></blockquote>

The assembler is pretty much free to name the register whatever it would want to. Im sure you could make a macro renaming all r0 references to RAX etc etc, or the assembler would support both naming schemes directly.

After all, the iportant thing is the binary code, not what the asm name of the instruction is ( or the register, for that matter).
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