The G5 and what it means for future Macs - Page 7

everyone should just keep in mind that this is apple. not the apple of the past, but the apple of today. underwhelming.

[quote]Originally posted by Programmer:
<strong>Despite the authority with which Eric DVH speaks, there is no official information about this chip -- just a lot of fast and loose speculaton.</strong><hr></blockquote>

Except <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655" target="_blank">this</a> of course.

[quote]Originally posted by Programmer:
<strong>Thus far I've seen no rumours about the PCI-X controller on the chip,</strong><hr></blockquote>

Like I said.

[quote]Originally posted by Programmer:
<strong>and this seems like an unlikely thing to do. Designing new processor chips (even modular ones) is expensive so its far more effective to have one system interface (RapidIO) and hang all other busses on that. Multiple PCI-X controllers could then be attached if you could work out the addressing issues.</strong><hr></blockquote>

They definitely could. but the current design has it onboard. but I think using something like RapidIO, PCI or HyperTransport for interfacing directly between the CPU and it's I/O chip is stupid. a dedicated short range bus like MPX(Only running much closer to. if not right at. the CPUs maximum throughput) is much smarter. that way a given CPU part doesn't have to be redesigned whenever a new bus is released. instead. only the seperate I/O chip need be swapped.

[quote]Originally posted by Programmer:
<strong>No, its because there is latency in the memory production process and demand is cyclical. Demand goes up, production eventually rises to meet demand, but then demand drops off and there is way too much supply. Prices are low, and production is reduced. Demand then climbs again, and supply is inadequate. Prices are then high. Read this: <a href="http://www.macedition.com/op/op_ram_20020410.php" target="_blank">http://www.macedition.com/op/op_ram_20020410.php</a> </strong><hr></blockquote>

I'm afraid this is mired in the same circular logic conundrum as the Macintosh itself. some fear pricing too low as it might lower profits too much. while some fear pricing too high as it might scare off customers that would compensate with their volume. while this is a choice for the RAM industry to make. I myself think sales volume in this case would justify lowering prices some.

[quote]Originally posted by Programmer:
<strong>As I said above, CPUs take a while to design and deliver... we'd rather not wait for a new CPU to get faster busses, right?</strong><hr></blockquote>

I was simply noting that AGP 8x is a fair ways off.

[quote]Originally posted by Programmer:
<strong>The day isn't far away.</strong><hr></blockquote>

I hope so.

[quote]Originally posted by Programmer:
<strong>Did you even bother to read Dorsal M's posts? You know, the guy who started this thread that did exactly what you just suggested?</strong><hr></blockquote>

OOPS! sorry, sorry. I wrote this from newest post to oldest. and forgot to revise this part when I got back to DorsalM's posts. as for DorsalM's opinion. all that's in his posts is facts(Or something like that ).

[quote]Originally posted by Programmer:
<strong>And local processor memory is a very valid concept, used in many kinds of systems -- for Apple to take a radical approach like that could be their first real attempt to differentiate the Mac in a long time.</strong><hr></blockquote>

It would also be incredibly stupid. I think the best compromise would be something to go between level 3 cache and main RAM. constricting main RAM to the daughterboard of a given CPU would be VERY BAD.

quote:

RapidIO scales up to 8MBps. by "Discussed". do you mean the one that will actually be on the very first G5 when it ships?

[quote]Originally posted by Programmer:
<strong>Yes -- as I said above, if you build things into the processor you run the risk of delaying improvements in the system until the next processor revision. And we all know Motorola's track record on that score.</strong><hr></blockquote>

Ok.

quote:

DDR 2700 is already onboard the G5. they've chosen. it's done. no turning back.

[quote]Originally posted by Programmer:
<strong>Uh huh... and you've proven this how? Dorsal's messages at the top of this thread talk about DDR333, but historically his machines have been very early prototypes -- either never destined for production, or a long way from it. Nonetheless, DDR2700 wouldn't surprise me at all in the next set of machines, its what I'm hoping for at a minimum.</strong><hr></blockquote>

Like I said.

[quote]Originally posted by Programmer:
<strong>Yes... but if somebody gives you the MHz, not the MBps then you need to know the bus width.</strong><hr></blockquote>

Yes. but you were saying(Or I thought you were saying) that conversion between Mbps and MBps should be done by dividing by the bus width of the device in question. instead of by the constant of 8.

The bus width(And clock frequency) of the device should only be in mind when trying to discern the true <a href="http://www.webopedia.com/TERM/d/data_transfer_rate.html" target="_blank">data transfer rate</a> of the device.

[quote]Originally posted by Programmer:
<strong>Or for the first time you can upgrade the memory in these machines, making them more upgradable. Plus you can upgrade their memory bandwidth by adding processors. Again, did you read Dorsal M's post? I'm not pulling this stuff out of thin air.</strong><hr></blockquote>

Yes. you're right. but the upgrade to memory bandwidth would only be half-way. as no individual device would actually be able to benefit from the higher bandwidth unless the technology outside the CPU advanced considerably. and other devices as a whole wouldn't be able to access it either unless you were using an incredibly fast switching bus. in which case you might as well just put it on the CPU in the first place. I still think a proprietary high speed bus between the CPU and a seperate I/O chip would be smarter.

quote:

The cache isn't SRAM.

[quote]Originally posted by Programmer:
<strong>Yes, it is. If it was just DDR SDRAM then the advantage of using it would be practically nil.</strong><hr></blockquote>

No it isn't. look anywhere you please on Apple's site. and it will always say "DDR SDRAM". and yes. the advantage of using it _is_ practically nil.

[quote]Originally posted by Programmer:
<strong>Earlier chipsets don't really have the pixel rate to support it.</strong><hr></blockquote>

Yes they do. these features are enabled on their wintel counterparts. and have been for years.

[quote]Originally posted by Programmer:
<strong>Its just not feasible these days.</strong><hr></blockquote>

Yup.

Eric,

i applaude Eric for his calmness in the face of such hostility.

that is all i can add to this thread as i don't even know enough to speculate. But thanks for the knowledge you guys are sharing, i am learning a lot.

Peace,
G

[quote]Originally posted by AirSluf:
<strong>That seems to be a trademark of his.</strong><hr></blockquote>

Like I said.

[quote]Originally posted by AirSluf:
<strong>When has Apple actually made a hard drive? The interface the manufacturer provides is whay everyone has to work with. Bridges are how you deal with it, always has been.</strong><hr></blockquote>

<a href="http://www.theapplemuseum.com/products/miscellaneous/storage/storage.html" target="_blank">Almost since they started</a> . seriously though. I probably phrased this wrong. what I meant was:

I wonder if anyone(Including Apple) will ever make drives that use a native firewire interface like SCSI and FC-AL do. instead of some stupid bridge chip.

quote:
This wouldn't effect the RapidIO. as the PCI-X controller is also on-chip.

[quote]Originally posted by AirSluf:
<strong>Now you're making stuff up or are about to be fired. Wait a sec you're a student on Monterey Bay that likes to post between 2 and 3AM local, so you're not working for Mot or Apple, I guess that leaves making it up. How's business as a night sys-admin (just a guess).</strong><hr></blockquote>

Let's just say I'm a night person. and as for the top secret security clearance required for knowledge about the G5s PCI controller. click <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=01M98655" target="_blank">here</a>. and don't blame me if you have to give a tissue sample prior to access.

[quote]Originally posted by AirSluf:
<strong>I think the originator meant people subscribing and watching HDTV. Broadcasters have to broadcast by law, doesn't mean lots of folks are watching. It's still a rich-boy toy technology when you have to spend $300+ on a HDTV receiver after you buy an already inflated HDTV "ready" television.</strong><hr></blockquote>

I think he meant whether or not an HDTV enabled piece of technology would be all that useful. and that $300 figure is a pack of lies(Also. some video chipsets. such as the GeForce2 MX. feature <a href="http://www.nvidia.com/Pages.nsf/Lookup/hdtv/$file/hdtv.PDF" target="_blank">latent HDTV decoder circuitry</a>. which would be substantially cheaper to activate than a whole separate tuner).

[quote]Originally posted by AirSluf:
<strong>Unless you live in a dorm, that doesn't make a lot of sense for mainstream customers. I have a decent sized TV for that and a computer for computing as most folks do. Spending money on a computer HDTV tuner under those circumstances is too much. Also, see again the last para on those HDTV "ready" TVs.</strong><hr></blockquote>

You've just touched on one of my pet peeves. this "The PC belongs in the office and the TV belongs in the living room" stuff is a nothing more than fearful propaganda and lies spread by the one-way computing industry in an attempt to retard progress. I have a decent sized monitor(20") that blows away any comparable TV in sharpness, color accuracy and pixel response, video projectors cost the exact same either way. and practically all video cards nowadays have RCA and S-Video out. I think Apple's "Digital Hub" philosophy isn't aggressive enough. why bother buying dozens of pieces of redundant hardware when you can just buy one highly flexible computer. which also beats the dedicated equipment on a one-to-one basis too.

Under those circumstances. spending money on an HDTV tuner is MUCH smarter than buying tons of overpriced, underfunctional equipment. next time you're going to upgrade your TV/stereo/home theater etc. consider going with an integrated PC approach(Although if you try to stay all-Mac. you won't be able to have HDTV, PVR functionality or 24-bit audio as of now. at least as far as I know). you'll save a lot of money. and gain quite a bit of flexibility.

[quote]Originally posted by AirSluf:
<strong>There you go again, add a smiley to deflect that you don't actually have a clue. What's the memory bandwith of a GF4Ti 4600? How about 10.6 GB/sec. I think it could easily require being fed 4-8GB/sec, if not close to the full bandwidth. And in the next 6-12 months those bandwidth numbers will very likely approach a doubling again. Geez, at least read SOMETHING before you espouse false knowledge! At least make it challenging to be countered.</strong><hr></blockquote>

What I was referring to was whether or not Apple will get ATI/nVidia to design a special RapidIO native card/chipset just for them. or if they'll just stick in another stupid AGP card/chipset like in current systems.

[quote]Originally posted by AirSluf:
<strong>This one takes the cake, well at least ties. Putting the memory controller directly on the chip allows you to put CPU memory access on a seperate bus.</strong><hr></blockquote>

And it also gets Apple into the same mess their in now. the best method is to put all frontside I/O(Including RAM and RapidIO) on a separate I/O chip. which is connected to the CPU using a proprietary high speed bus. which runs as close to the CPUs total throughput as possible.

[quote]Originally posted by AirSluf:
<strong>Far future my ___, and more of the phantom definite specs.</strong><hr></blockquote>

Like I said.

[quote]Originally posted by AirSluf:
<strong>As a build to order option great idea, but don't make everyone pay for dorm room convienience. Probably the same basic line of reasoning reason you don't like monitors with tuners. You always have to pay for it and the implementation has limitations.</strong><hr></blockquote>

Apple includes a $10 mic in the all of their machines other than the PowerMac G4. I think people would appreciate something like this. and the reason I don't like monitors with tuners is because real TV tuners are better interfaced with the computer. allowing things like PVR functionality and WaveTop . and they(Monitors with tuners in them) perpetuate the myth that real TV tuners don't exist.

[quote]Originally posted by AirSluf:
<strong>DOH! This one takes the cake! Didn't you even READ Dorsals post that started the whole thread!</strong><hr></blockquote>

OOPS! sorry, sorry. I wrote this from newest post to oldest. and forgot to revise this part when I got back to DorsalM's posts.

[quote]Originally posted by AirSluf:
<strong>You have also missed the meaning of most of the technical discussions (that followed that first post) on how it seems to fit together. More spouting off without a solid technical bacground to fall back on.</strong><hr></blockquote>

I was merely pointing out the shortfalls of such a design choice.

[quote]Originally posted by AirSluf:
<strong>And you have this special factual knowledge nobody else is openly discussing how? You're no Worker Bee.</strong><hr></blockquote>

Like I said.

[quote]Originally posted by AirSluf:
<strong>Maybe, maybe not. That is an implementation specific detail.</strong><hr></blockquote>

Let's just say it's highly unlikely that Motorola would choose a low-end DDR controller

[quote]Originally posted by AirSluf:
<strong>That would be right except for the fact that you're wrong. Wrong context, if you are takling throughput. Another simplistic error made due to lack of basic knowledge.</strong><hr></blockquote>

No. you _never_ take the bus width or clock speed of a device into account unless trying to determine true <a href="http://www.webopedia.com/TERM/d/data_transfer_rate.html" target="_blank">date transfer rate</a> of it. 8 bits per byte is _always_ valid in all other cases.

[quote]Originally posted by AirSluf:
<strong>Putting RAM slots on a daughterboard is hardly everything.</strong><hr></blockquote>

Sure it is. read my post.

[quote]Originally posted by AirSluf:
<strong>What CPU upgrades are available that are worth paying for on a desktop Mac less than four years old. I thought so, none.</strong><hr></blockquote>

And this would make it better!?

[quote]Originally posted by AirSluf:
<strong>Did you see that paragraph is talking about Level 3 cache? Did you stop to think the level 2 cache might be SRAM?</strong><hr></blockquote>

The original poster wasn't referring to level 2 cache:

[quote]Originally posted by MarcUK:
<strong>If there is no such thing as DDR 400MHZ, could someone tell me what the 500MHZ DDR L3 Cache in the Dual Tower is. I really don't know</strong><hr></blockquote>

[quote]Originally posted by AirSluf:
<strong>Didn't think so. DDR SDRAM Level 3 just adds another layer of cache for when the fast on-chip L1 & L2 caches both miss. Again, read. But first learn enough so you can understand what you are reading in the correct context. If you did that you would recognize Apple is already doing what you propose and more. Quit talking out your ass sideways.</strong><hr></blockquote>

No they're not. Apple is moronically using dynamic RAM for CPU cache. I'll always hate the dolt(s) responsible for this unless they switch back to SRAM.

[quote]Originally posted by AirSluf:
<strong>The framerate hits are astounding on the older hardware.</strong><hr></blockquote>

Yeah right. FSAA for example only has a 2x-4x(Depending on what level of oversampling you're using) speed hit. I think I'd pay that gladly(Especially with Escape From Monkey Island!).

[quote]Originally posted by AirSluf:
<strong>Isn't that what I said without adding all the other processor types in? I also think that's one of the specs in the Book-E book that some of us have seen and commented on in this and previous threads.</strong><hr></blockquote>

I was merely clarifying your point by adding that Apple wouldn't have to make OS X 64-bit aware in any significant way.

Eric,

[quote]Originally posted by jgroth:
<strong>Regarding FSAA:
The framerate hits are just WAY too much unless you have a fantastic system (top of the line PC, GF4 and all ).</strong><hr></blockquote>

Not really. FSAA for example only has a 2x-4x(Depending on what level of oversampling you're using) speed hit. I think I'd pay that gladly(Especially with Escape From Monkey Island!).

[quote]Originally posted by jgroth:
<strong>But...it's not really necessary at resolutions above 800x600. At higher resolutions, the 'jaggies' start to fade. I run 1024x768 on my G4 400 Sawtooth (Radeon, 1.4GB RAM), the 'jaggies' are hardly noticable and I average over 60fps on the Quake 3 "demo four."

The smaller everything is (due to resolution), the less noticable they are. At least, I think so.</strong><hr></blockquote>

The jaggies start to fade. yes. but other things still look awful. like the moiré effect caused by pixelated patterns such as the audiences in racing games and text(On screens and signs). especially when viewed at an extreme angle. bump mapping looks particularly horrible without it. just pop open any 3D animation program that's capable of oversampling. and render a complex(Preferably heavily bump mapped, with lots of repetative textures and reflections on curved surfaces) scene both with and without it. some scenes are impossible to do well without oversampling. animation generally excruciates this.

Eric,

[quote]Originally posted by Stoo:
<strong>The book E compliant CPU on Moto's website (8[45]xx?) lists DDR 333 RAM, which I suppose is PC2700. Perhaps it's they == Mac rumourists have chosen and decided that this is definitely a G5
, and AIM had better not turn back </strong><hr></blockquote>

If they do release a PowerMac G5 with less on it than the 8540. I doubt they'll ever hear the last of it.

[quote]Originally posted by Stoo:
<strong>Pop your proto-G5 case open and watch as you or your organisation never gets one again...</strong><hr></blockquote>

We'll just see if DorsalM ever posts new info again.

[quote]Originally posted by Stoo:
<strong> :eek: </strong><hr></blockquote>

If they mess with it. a multiprocessing system would just roll over on it's back and lie there.


Eric,

about performance did you compare the 7455 with the 8540 on moto web site?
it's this:
G4 @ 1Ghz = 2310 MIPS
8540 @ 1Ghz = 2315 MIPS

so if the 8540 = G5, the only 'snappier' thing will be : DDR-ram, Rapid-IO, etc...
Not the processor <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />

No? Maybe i'm wrong on this

Keep in mind that the 8540 as no L3 cahe and no altivec

[ 04-24-2002: Message edited by: jeromba ]</p>

me being stupid

[ 04-24-2002: Message edited by: Strangelove ]</p>

[quote]Originally posted by haderach:
<strong>Yesterday I had access to a document discribing the Motorola MPC7400 processor. [ 04-19-2002: Message edited by: haderach ]</strong><hr></blockquote>

Thanks for the real info Haderach, there's a few too many people 'round these parts who prefer making up their own information rather than gathering the real stuff ... hey, Mia Culpa.

Nice to see somebody doing a bit of real research ... I rarely have the time ...

.... and now on to my G7 and "Elvis-As-The-Second-Coming" concepts ...

[quote]Originally posted by Eric D.V.H:
<strong>looks </strong><hr></blockquote>
is it just me or is this form of arguement particularly annoying?
[quote]Originally posted by Eric D.V.H:
<strong>particularly</strong><hr></blockquote>
See, "particularly" for example - doubling back on itself.
[quote]Originally posted by Eric D.V.H:
<strong>horrible without</strong><hr></blockquote>
Without context most sentences become weaker and harder to defend, so much so that people end up ignoring a total arguement for the fight over half a sentence.
[quote]Originally posted by Eric D.V.H:
<strong>looks particularly horrible without it. just</strong><hr></blockquote>
I stopped reading this kind of "dialog" a long time ago. It usually indicates a usually pissy approach.

<strong>Originally posted by AirSluf:
You're right, Level 3 cache is DDR SDRAM.</strong>

Hell, I'm not even going to believe this, that the backside cache is DDR SDRAM, until someone pops off the heat sink of their 2002 Power Mac and takes a picture. So, I will continue to believe that the Power Macs have DDR SRAM until proven otherwise. Not to mention that the Power Mac developer note says its SRAM either.

<strong>Originally posted by jeromba:
about performance did you compare the 7455 with the 8540 on moto web site?
it's this:
G4 @ 1Ghz = 2310 MIPS
8540 @ 1Ghz = 2315 MIPS

so if the 8540 = G5, the only 'snappier' thing will be : DDR-ram, Rapid-IO, etc...
Not the processor <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />

No? Maybe i'm wrong on this</strong>

Yes, you are wrong in this. Because you forgot the part about the 1 GHz 8540 being a 0.13 micron (HiP 7) part while the 1 GHz 7455 G4 is a 0.18 micron (HiP 6 + SOI) part. So, if both processors are fabbed on the some process, the G4 will clock 30% higher than the 8540 making it always faster, by a considerable amount.

<strong>Keep in mind that the 8540 as no L3 cache and no altivec</strong>

It doesn't have an FPU either. It does have some sort of new and more DSP specific integer SIMD though. Not AltiVec.

[ 04-24-2002: Message edited by: THT ]</p>

There is no evidence that Apple will use the 8540 -- it is specifically targetted at the embedded market. The G5 that Apple will use may use the eCore (hopefully a much faster variation of it), but the PCI-X controller, dual DUARTS, and the on-chip 10/100 Ethernet controller will likely not be present... they aren't part of the eCore, they are representative of the new design's modularity. Its possible that the 10/100/1000 Ethernet controller could be placed on the processor (like the 8540), but this limits Apple's choice of Ethernet controllers. With the RapidIO bus there is no reason to do this, and there are better things to build into a desktop processor (like larger caches, a better memory controller, more execution units, etc). Still, the option is there for on-chip USB and FireWire controllers -- time will tell.

I think you've missed the whole point about RapidIO and HyperTransport -- they are improved replacements for wide busses like the MPX. The MPX is expensive and limited in performance & flexibility. It is currently 64-bits wide and 133 MHz, and pushing the design might get it to 128-bits wide or 200 MHz (probably not both). DDR may be added. It is hard to build boards for the current design, and harder for an improved version. The means it might get to about 4 GB/sec, maximum, with an expensive board. RapidIO is already spec'd up to ~7.5 GB/sec (see RapidIO.org's FAQ), and HyperTransport to 12.8 GB/sec. They are narrower so it easier to interface narrower devices to them (and those devices will perform much better due to the higher clock rates), there are far fewer pins and it is much easier to build boards that can carry their signals. These new serial busses are specifically designed to replace things like the MPX so that processors can interface with things like their I/O chipsets. This isn't stupid, it is very smart and it is the future of motherboard design. You'd better get used to it.

[quote]
&lt;&lt;w.r.t. RAM commodity market&gt;&gt;
I'm afraid this is mired in the same circular logic conundrum as the Macintosh itself. some fear pricing too low as it might lower profits too much. while some fear pricing too high as it might scare off customers that would compensate with their volume. while this is a choice for the RAM industry to make. I myself think sales volume in this case would justify lowering prices some.
<hr></blockquote>

Well perhaps a few courses in economics and a dose of reality will help you understand the real world instead of your idealized fantasy world. There are many more factors involved in this and yet you lump them all together and call it price gouging.

[quote]
&lt;&lt;w.r.t. local memory per processor&gt;&gt;
It would also be incredibly stupid. I think the best compromise would be something to go between level 3 cache and main RAM. constricting main RAM to the daughterboard of a given CPU would be VERY BAD.
<hr></blockquote>

:shrug: Go do some research into supercomputers and other advanced architectures, and then tell those guys that they are being stupid. Also, remember that RapidIO is faster than the MPX bus so taking this approach just might not be as bad as you seem to think. For larger interactions, OSX already a virtual memory system so using the DMA engines to implement paging between processors isn't out of the question.

[quote]
DDR 2700 is already onboard the G5. they've chosen. it's done. no turning back.
<hr></blockquote>

Its in the 8540, yes. Does that limit what is in a desktop version? No.

[quote]
Yes. but you were saying(Or I thought you were saying) that conversion between Mbps and MBps should be done by dividing by the bus width of the device in question. instead of by the constant of 8.
<hr></blockquote>

No, somebody had been talking about GPU memory clock rates, IIRC. Crossed conversations again.

[quote]
...unless you were using an incredibly fast switching bus....
<hr></blockquote>

RapidIO, perhaps?

[quote]
The cache isn't SRAM.
<hr></blockquote>

<a href="http://developer.apple.com/techpubs/hardware/Developer_Notes/Macintosh_CPUs-G4/PowerMacG4/2Architecture/Cache_Memory.html" target="_blank">PowerMac G4 Cache Memory</a>

Okay, you're right on that one. Its even more of a lame cop-out than I thought. It really disturbs me that nVidia can ship $500 graphics boards with 650 MHz DDR memory, and Apple can't afford to put a decent 2 mbytes L3 cache on its machines.

Hopefully the L3 cache will disappear in future machines. Making the on-chip (thus 1GHz+) L1/L2 caches much larger would be more effective. Having the memory controller on-chip makes this likely as it would replace the L3 cache controller. Having both would really bloat the pin count.

[quote]
&gt;&gt;Originally posted by Programmer:
&gt;&gt;Earlier chipsets don't really have the pixel rate to support it.
Yes they do. these features are enabled on their wintel counterparts. and have been for years.
<hr></blockquote>

Well for the game you quote it would be okay (Monkey Island). For anything which is actually pixel rate bound it will cut your framerate at least in half. On the PC the FSAA switch is often in a user control panel outside of the game, and the game knows nothing about the change (which causes problems with some games).

I do hope that Apple lets ATI/nVidia add OpenGL extensions to get at these features, or (better) defines extensions for them both to implement the same way to get at these features. I know they are working on some things, but I don't know how extensive their efforts are.

[ 04-24-2002: Message edited by: Programmer ]

[edited overlong URL -Amorph]

[ 04-25-2002: Message edited by: Amorph ]</p>

[quote]Programmer
The cache isn't SRAM.

<a href="http://developer.apple.com/techpubs/hardware/Developer_Notes/Macintosh_CPUs-G4/PowerMacG4/2Architecture/Cache_Memory.html" target="_blank">PowerMac G4 Cache Memory</a>

Okay, you're right on that one.<hr></blockquote>

Now, I'm confused(re: this can be easily done by the way.)

This directly conflicts with the following Motorola link.

<a href="http://e-www.motorola.com/collateral/SNDFH1112.pdf" target="_blank">http://e-www.motorola.com/collateral/SNDFH1112.pdf</a>

look at page 6.

It clearly states,
"256kB on-chip L2 + 2 MB backside L3
DDR SRAM support on L3"

Did Apple ask Motorola to implement DDR SDram instead of what this document clearly states the G4 7450 supports?? <img src="graemlins/surprised.gif" border="0" alt="[Surprised]" /> <img src="graemlins/surprised.gif" border="0" alt="[Surprised]" /> <img src="graemlins/surprised.gif" border="0" alt="[Surprised]" />

[ 04-24-2002: Message edited by: rickag ]

[edited overlong URL -Amorph]

[ 04-25-2002: Message edited by: Amorph ]</p>

Eric D.V.H. wrote:

[quote]Originally posted by AirSluf:
When has Apple actually made a hard drive? The interface the manufacturer provides is whay everyone has to work with. Bridges are how you deal with it, always has been.

<strong>Almost since they started &lt;http://forums.appleinsider.com/cgi-bin/smile.gif&gt; . seriously though. I probably phrased this wrong. what I meant was:

I wonder if anyone(Including Apple) will ever make drives that use a native firewire interface like SCSI and FC-AL do. instead of some stupid bridge chip.
</strong><hr></blockquote>

Actually, Apple has never made any drive mechanisms - HDD, optical, floppy or otherwise. They have always bought the mechanism from someone else and repackaged it (ditto cameras, printers, scanners, etc.). In the case of the old SCSI and DB-19 devices, they also replaced the default ROM with a custom Apple ROM. But the HDD itself came from Seagate, or Quantum, or IBM, or whoever.

I can't remember whether it was Western Digital or Maxtor who had announced that they had developed a native FW hard drive a while back, but they didn't seem to find any takers. IDE drives are so cheap, and the Oxford 911 bridge chipset performs well enough at a good enough price, that they're not worth it.

I wouldn't mind a native FW drive right now, either, after an evening spent trying to get an IDE drive in a FW case to work, and failing. But unless Apple essentially decides to fund the effort, and buy lots of them, I don't see them appearing in the near future, if at all.

[ 04-24-2002: Message edited by: Amorph ]</p>

[quote]Originally posted by AirSluf:
<strong>Thanks for the link rick. The DDR SDRAM fiasco created by the info on Apples developer web site (last updated 16 Jan) is the only thing I have seen directly putting the issue in black and white until now.

THT, I sympathise, but since the last time I saw this issue flare up, either nobody cared enough to actually check their box, or they didn't like the answer (hopefully the former). The developer note does say DDR SDRAM though:



Only problem now with thinking the L3 cache is SRAM is the page that has the L3 cache description still says updated 16 Jan and still says DDR SDRAM. (same in the available PDF) WTF? Did it get updated or not?

THT, do you have some Apple hardcopy that has a little more care taken in it's writing?

[ 04-24-2002: Message edited by: AirSluf ]</strong><hr></blockquote>


ooops, FYI
posted March 13, 2002 00:16 Â*
------------------------------------------------------------------------

quote:
------------------------------------------------------------------------
According to JfW, SDRAM is a typo, so DDR SRAM at 500MHz data rate. The point being that... Apple has a 4:1 clock rate on the new GHz, but claim to feed the CPU at 2:1 data rate?
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Right... The SRAMs on the newer machines are MSUG2 DDR SRAMs (Samsung I believe as Motorola no longer produces those)
As for the timings, that's correct as well. With the DDR SRAMs, they run at 1/4 the core clock. So if you have a 1GHz CPU (fCORE=1000Mhz) then the fL3_CLK=250Mhz. In DDR mode the '50+ processors read 2 FIFO entries per successive core clock, so you can get throughput of 500Mhz SRAMs. The one caveat is that L3 data can't be sampled until second beat of data is validated so you're hit with essentially an L3 half-clock of read latency, however the throughput makes up for it.

from arstechnica -URL won't copy and too long to type

Does any one have ideas on when or if Apple will ever use Rapid I/O or any of the technology represented on the Product Information sheet for the MPC8540.

I now have an uneasy feeling that this tech may be a long, long way off for Apple.

Dorsal is <a href="http://www.altairiv.demon.co.uk/troll/trollfaq.html" target="_blank">trolling</a> us, and doing a good job with it at that.

My hat's off to him.

<strong>Originally posted by AirSluf:
Only problem now with thinking the L3 cache is SRAM is the page that has the L3 cache description still says updated 16 Jan and still says DDR SDRAM. (same in the available PDF) WTF? Did it get updated or not?</strong>

It got updated. At least the PDF did. The version I downloaded in January says DDR SRAM.

<strong>THT, do you have some Apple hardcopy that has a little more care taken in it's writing?</strong>

No.

The problem is that there needs to be explicit support for memory types, and the Moto 7455 documentation still says SRAM support only. The issue would simply be settled if someone, actually more than 1 person, took the heat sink of their new PowerMacs and have a look see. xlr8yourmac.com usually finds someone that does this, but this time around, I haven't seen any. Maybe it's there and I missed it though.

[ 04-25-2002: Message edited by: THT ]</p>

[quote]something to go between level 3 cache and main RAM<hr></blockquote>

L4 cache?

Should have said "open your G5 case without being allowed to"

Anyone got links to what Book E actually is and what it covers?

[ 04-24-2002: Message edited by: Stoo ]</p>

[quote]
Dorsal is trolling us, and doing a good job with it at that.

My hat's off to him.
<hr></blockquote>

Oh. Yah. Because it's so massively hard to troll in the AI boards.
-Short Bus Driver

[quote]Originally posted by *l++:
<strong>Dorsal is <a href="http://www.altairiv.demon.co.uk/troll/trollfaq.html" target="_blank">trolling</a> us, and doing a good job with it at that.

My hat's off to him.</strong><hr></blockquote>


Thank you. Someone has some sense around here it would seem.

I've always been skeptical of Dorsal, and I picked up on his M.O. in a few minutes. He predicts every possible upgrade that Apple could implement, and then after the upgrade he can point to his prediction and claim that it was dead on.

Uh, no. If I predict that tomorrow it will either be sunny, or cloudy, or cloudy and rainy, or sunny and rainy, and then on the next day it happens to be sunny, that doesn't necessarily mean that my prediction was reliable. The only difference between this example and Dorsal's predictions is that he is extremely well versed in bleeding edge computer tech, so his predictions represent all of the possible outcomes.

i hope you guys haven't scared Dorsal away...

[quote]Originally posted by Amorph:
<strong>Eric D.V.H. wrote:
Actually, Apple has never made any drive mechanisms - HDD, optical, floppy or otherwise.</strong><hr></blockquote>

I'm quite certain this is incorrect.

Apple spent a gigantic amount of money building a factory to create the 5.25" "Twiggy" CLV floppy disks that were in the Lisa.

The factory yield was less than 5%, IIRC. The book I read, West of Eden, said they wasted over $1 billion on the factory effort.

[quote]Originally posted by Short Bus Driver:
<strong>Oh. Yah. Because it's so massively hard to troll in the AI boards.
-Short Bus Driver</strong><hr></blockquote>

Gee, I thought every new thread in this forum was a "trolling" attempt. Its kind of the whole point of a future hardware discussion group.

So the verdict on the L3 cache memory is that I was right and it is SRAM, not SDRAM? Good, even Apple couldn't be that stupid (documentation errors not withstanding).

Apple has clearly stated that the new L3 cache where DDRAM, if this info they gave is incorrect then it would be false advertising. I don't know the law in US , but In France it's illegal and you can be sued for this.

[quote]Originally posted by powerdoc:
<strong>Apple has clearly stated that the new L3 cache where DDRAM, if this info they gave is incorrect then it would be false advertising. I don't know the law in US , but In France it's illegal and you can be sued for this.</strong><hr></blockquote>

DDR simply means data is transfered on the leading and trailing edges of the clock signal. Both SDRAM and SRAM can be built to do this. I have no doubt that the L3 is using DDR, the question is whether it is using SDRAM, or SRAM. Their documentation seems to say SDRAM in most places, but this doesn't make much technical sense -- SRAM would be much more effective. I suspect it is just the that their technical writers never heard of SRAM and thus were "correcting" the documents... or the spelling checker doesn't have an entry for SRAM, just SDRAM, and it was being helpful. I've seen this happen a few times.

[quote]Originally posted by Junkyard Dawg:
<strong>
I've always been skeptical of Dorsal, and I picked up on his M.O. in a few minutes. He predicts every possible upgrade that Apple could implement, and then after the upgrade he can point to his prediction and claim that it was dead on. </strong><hr></blockquote>

You act like this is some sort of contest. Your comments say a lot more about you than about Dorsal.

Dorsal doesn't "predict" what Apple will release: he simply reports the hardware he's seen and how well it works. He may offer a guess as to how mature the technology is and therefore how soon it could come to market, but he claims no insider information as to what Apple is actually planning to release, or when.

Secondly, I don't recall Dorsal ever gloating over any of his predictions being borne out. If he's here to pump his ego, he's being awfully mellow about it.

Like a lot of people here, you seem very paranoid about being trolled. Lighten up and actually read what Dorsal posts without projecting too many of your own anxieties onto it.

[quote]Originally posted by Tom Mornini:
<strong>

I'm quite certain this is incorrect.

Apple spent a gigantic amount of money building a factory to create the 5.25" "Twiggy" CLV floppy disks that were in the Lisa.

The factory yield was less than 5%, IIRC. The book I read, West of Eden, said they wasted over $1 billion on the factory effort.</strong><hr></blockquote>

That neatly explains why they never tried building a mechanism again, doesn't it?

Thanks for the clarification.

<a href="http://zdnet.com.com/2100-1103-892187.html" target="_blank">http://zdnet.com.com/2100-1103-892187.html</a>

This sort of thing really makes me want to stay with Intel. I have a good understanding of what will be available over the next year.

I'm holding back from any further Apple purchase because I have no idea what's coming from Apple. If Intel is at 3Ghz by December with a 533Mhz bus and 1066Mhz RDRAM for LESS $$$ than a 1.6hz G5 (even if it's 5% faster than the Intel), forget Apple, fewer dollars on equipment means more in my pocket for living my life.

Yeah XP sucks donkey but OS X has it's crappy aspects as well, and since I can't get a high resolution screen from Apple without selling the farm, I can spend the time on learning to disable Passport in the XP registry.

Oh I don't know!!! it's all so silly.

[quote]Originally posted by Programmer:
<strong>

DDR simply means data is transfered on the leading and trailing edges of the clock signal. Both SDRAM and SRAM can be built to do this. I have no doubt that the L3 is using DDR, the question is whether it is using SDRAM, or SRAM. Their documentation seems to say SDRAM in most places, but this doesn't make much technical sense -- SRAM would be much more effective. I suspect it is just the that their technical writers never heard of SRAM and thus were "correcting" the documents... or the spelling checker doesn't have an entry for SRAM, just SDRAM, and it was being helpful. I've seen this happen a few times. </strong><hr></blockquote>
Ha yes i see. Read too quickly that thread ...I think it's rather DDR SRAM, because i never eard of 500 mhz DDR SDRAM (on a graphic card they will talk of 1000 mhz memory : 500 * 2)

[quote]Originally posted by Tom Mornini:
<strong>

Apple spent a gigantic amount of money building a factory to create the 5.25" "Twiggy" CLV floppy disks that were in the Lisa.

The factory yield was less than 5%, IIRC. The book I read, West of Eden, said they wasted over $1 billion on the factory effort.</strong><hr></blockquote>

Hey, that's exactly the chapter I'm on in Michael Malone's "Infinite Loop". Has a great little anecdotal story about how the Mac team kept hiding one of Sony's disk drive engineers everytime Jobs would pay a visit.

"This sort of thing really makes me want to stay with Intel. I have a good understanding of what will be available over the next year.

I'm holding back from any further Apple purchase because I have no idea what's coming from Apple. If Intel is at 3Ghz by December with a 533Mhz bus and 1066Mhz RDRAM for LESS $$$ than a 1.6hz G5 (even if it's 5% faster than the Intel), forget Apple, fewer dollars on equipment means more in my pocket for living my life."

G5, whither art thou?

Lemon Bon Bon

Some notes from a source I trust - Take them with all the salt your diet requires:

WWDC - No hardware. Software event.

MWNY - 1gig G4 133Mhz bus $1449 256 MB RAM

1.2 gig G4, 512 DDR (266) RAM around $2100
1.4 gig G4, 1gig DDR (266) RAM around $3000

Dualies possible, but unknown.

New Powerbooks April 30. Source claims 867 Mhz with DDR RAM. And new Graphics subsystem.

If Apple has a DDR compatible G4 for the PowerBook, it might make a good test bed for the new mobo (since Apple tends to have unified motherboards nowadays).
They put it in a highly-profitable machine and it kicks BUTT, creating lots of demand.... Hmm. time to buy some more stock.

Whatcha think?

Sounds reasonable.

The biggest surprise is the possibility that the PB would get DDR RAM first?! If that's true, the portable crowd will be crowing for months.

I actually wouldn't be shocked if the mid- and high-end were duallies, or if they all were. That would turn the top of the line into the bottom of the line (modulo RAM and drive choices) which Steve is fond of doing.