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The G5 and what it means for future Macs - Page 2

post #41 of 357
<strong>Originally posted by MaCommentary:
1) Wasn't there a rumor going around that Apple would call the 7500 the G5 even though it's really just a G4 with some G5 features? I mean remember that the original G4 was a G3 with an altivec unit on it.</strong>

The original Motorola roadmap had the G5 as a 7500 processor. It's only last Fall that Moto changed the roadmap to the current and confusing one. Previsouly, Moto's embedded processors had numbers of 8xxx and G4 processors had numbers of 74xx. All that has been shot to hell now. What I'm saying is that the marketing numbers are irrelevant.

<strong>2) One interesting thing about Dorsal's post was the RapidIO running @ 500MHz. To my knowlegde, the HyperTransport consortium has only gone public with speeds up to 400 MHz. Apple is one of it's strongest players though, and I wouldn't be supprised if they had internal tests going on with higher speed RapidIO.</strong>

Both HT and RapidIO have to scale to 1 GHz clock rates to achieve superior bandwidth. The 500 MHz number is logical if not necessary. Considering that RapidIO, the 16 bit wide version, delivers 4 bytes per clock and at 500 MHz only delivers 2 GByte/s, that's barely enough to support main memory. No wonder there is a memory controller on the CPU die.

<strong>3) I may have heard wrong, but when your memory goes at 333MHz or 400MHz that L3 cache is really not needed.</strong>

You heard wrong. Now, cost could be a completely different issue. Ie, L3 cache won't gain you that much for the cost, so it won't be necessary from that standpoint, but main memory technologies won't be catching up to processor performance in the near future and a multi-cache design has its benefits.
post #42 of 357
[quote]Originally posted by Eugene:
<strong>

Anyway, at least kormac tried a bit harder. Either kormac was from Korea or he spent some time looking for a korean proxy server. And kormac's speculation was a lot more entertaining.

And if you scrutinize some parts of e-www.motorola.com, it's not hard to figure out why one would believe in the existence of an MPC7500.</strong><hr></blockquote>

Ah the glory of obfuscated opinions. Nice on Eugene! It took me 2 looks at it before it hit home.
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post #43 of 357
Dorsal's specs look like <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=02M0ylfVS0lM9 43030450467M98655" target="_blank">this.</a>
post #44 of 357
This is interesting....

I did a <a href="http://search.motorola.com/semiconductors/query.html?col=corp&col=sps&col=mcg&charset=iso-8859-1&ht=0&qp=&qt=64bit+7500&qs=&qc=&pw=100%25&ws=1&la =en&qm=0&st=1&nh=25&lk=1&rf=0&rq=0&si=0" target="_blank">search</a> for 64bit 7500 at motorola's site. Look at the first 2 results,

frontmat
BTS Optimization/ATP CDMA LMF Software Release 15. X SC 611 1.9 GHz and 800 MHz CDMA English Sep 2000 68P64114A843 FOA Notice While reasonable efforts have been made to assure the accuracy of this ...
<a href="http://ted.motorola.com/CDMA/documentation/productdoc/FOA/114a84-3.pdf" target="_blank">http://ted.motorola.com/CDMA/documentation/productdoc/FOA/114a84-3.pdf</a> - 7790.2KB - 7500: 4

binder
1.9 GHz and 800 MHz CDMA 68P64114A43O BTS Optimization/ATP SC 611 TECHNICAL EDUCATION & DOCUMENTATION PREMIER GLOBAL INFORMATION PROVIDER CDMA LMF Software Release 2.8.x and 2. ...
<a href="http://ted.motorola.com/CDMA/documentation/productdoc/GA/114a43-o.pdf" target="_blank">http://ted.motorola.com/CDMA/documentation/productdoc/GA/114a43-o.pdf</a> - 2038.8KB - 7500: 4

They are password protected so I was not able to access them...


Actually I think that this has something to do with their cell phones... <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
I might be wrong though.

[ 03-20-2002: Message edited by: imacman287 ]</p>
post #45 of 357
[quote]Originally posted by imacman287:
<strong>This is interesting....

I did a <a href="http://search.motorola.com/semiconductors/query.html?col=corp&col=sps&col=mcg&charset=iso-8859-1&ht=0&qp=&qt=64bit+7500&qs=&qc=&pw=100%25&ws=1&la =en&qm=0&st=1&nh=25&lk=1&rf=0&rq=0&si=0" target="_blank">search</a> for 64bit 7500 at motorola's site. Look at the first 2 results,

frontmat
BTS Optimization/ATP CDMA LMF Software Release 15. X SC 611 1.9 GHz and 800 MHz CDMA English Sep 2000 68P64114A843 FOA Notice While reasonable efforts have been made to assure the accuracy of this ...
<a href="http://ted.motorola.com/CDMA/documentation/productdoc/FOA/114a84-3.pdf" target="_blank">http://ted.motorola.com/CDMA/documentation/productdoc/FOA/114a84-3.pdf</a> - 7790.2KB - 7500: 4

binder
1.9 GHz and 800 MHz CDMA 68P64114A43O BTS Optimization/ATP SC 611 TECHNICAL EDUCATION & DOCUMENTATION PREMIER GLOBAL INFORMATION PROVIDER CDMA LMF Software Release 2.8.x and 2. ...
<a href="http://ted.motorola.com/CDMA/documentation/productdoc/GA/114a43-o.pdf" target="_blank">http://ted.motorola.com/CDMA/documentation/productdoc/GA/114a43-o.pdf</a> - 2038.8KB - 7500: 4

They are password protected so I was not able to access them...


Actually I think that this has something to do with their cell phones... <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
I might be wrong though.

[ 03-20-2002: Message edited by: imacman287 ]</strong><hr></blockquote>

You do realize that 1.9GHz and 800Mhz are not chip speeds, but the frequencies that cell phones operate at?
post #46 of 357
I do now after fishing around on mot's site some more... What was I thinking (I guess we all want a 1.9Ghz G5...) <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />
post #47 of 357
[quote]Originally posted by imacman287:
<strong>Dorsal's specs look like <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=02M0ylfVS0lM9 43030450467M98655" target="_blank">this.</a></strong><hr></blockquote>

They share a couple of similarities... but so would any advanced chip, especially one designed by the same company!

My biggest concern about these specs (if true) is that the AGP/PCI bus would be across the RapidIO bus which, as pointed out by THT, tops out at around 2 GBytes/sec in the specified configuration. That could be a bit limiting if the I/O system is doing memory operations across the RapidIO bus (which it has to do now since the memory controller is on the chip). Hopefully the RapidIO bus on this chip can be scaled quickly to higher rates. Still, it would be a big step up from the current systems.
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post #48 of 357
[quote] ...AGP/PCI bus would be across the RapidIO bus... <hr></blockquote>

Let's do a real quick thought experiment.

Assume that the CPU and RAM are on a daughterboard, and the AGP/PCI busses are all on the motherboard.

In current designs (CPU on daughterboard, RAM on motherboard), there's one big bus which connects the CPU to the RAM to the AGP/PCI, which is shared amongst them.

In the design above (RAM on daughterboard), now our one big bus only has to connect daughterboard to AGP/PCI (plus secondary busses like IDE/Firewire/USB, etc).

So in current designs, our bandwidth is shared, with lots of chances for contention, where one device (say RAM) needs the bus a lot more often than other devices (say Firewire).

But in the newer design, without the RAM causing bus contention, the bus bandwidth doesn't need to be as big- since CPU-to-RAM communication is off of it!

Further, with this in mind, what's the max bandwidth of 4x AGP? 1 GB/s. What's the max bandwidth of PCI? 133 MB/s. What's the max bandwidth of Firewire? 50 MB/s. In other words, all these secondary devices are less than the 2 GB/s offered by a 500 MHz 16-bit bus.

What will be interesting is, what's the bandwidth between CPU and DDR RAM? Will Apple opt for a Workstation-class 128-bit DDR bus, or will they go industry-standard 64? What about implementing multiple channels of DDR RAM (assuming the G5's presumed built-in DDR controller supports it), the way Via/Intel etc. are going?

Just a few thoughts,

-HOS
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post #49 of 357
[quote]Originally posted by HOS:
<strong>

What's the max bandwidth of PCI? 133 MB/s.

-HOS</strong><hr></blockquote>

The max bandwidth of the PCI of the powermac G4 on 133 mhz mobo is 215 MB/s, it's 64 bit bus PCI.

Anyway your thoughts are very interesting, the existence of two bus : one especially for the ram and the others for PCI bus, and others, can bring overall performance to the system.
If the 2 GB/s bandwidth is fully use, it will make a big difference with a 2 GB/s bandwidth from the PC world.
post #50 of 357
the max bandwidth for firewire is 400Mb/s
max bandwidth for firewire2 is 800Mb/s

i think...actually am pretty sure.
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post #51 of 357
[quote]Originally posted by g::masta:
<strong>the max bandwidth for firewire is 400Mb/s
max bandwidth for firewire2 is 800Mb/s

i think...actually am pretty sure.
Peace,
G</strong><hr></blockquote>

Firewire2 (aka 1394b) starts at 800Mbps and goes up to 3.2Gbps depending on the cable type (copper, plastic optical, glass optical fiber).
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post #52 of 357
[quote]Originally posted by g::masta:
<strong>the max bandwidth for firewire is 400Mb/s
max bandwidth for firewire2 is 800Mb/s</strong><hr></blockquote>

You do know the difference between a bit and a byte, don't you? 800Mb/s is only 100MB/s.

What you might need at maximum:

- 1GB/s AGP
- 4*215GB/s 64-bit PCI = 860MB/s
- 100MB/s Firewire2
- 60MB/s USB 2

Total = 2020MB/s

Assuming that you will probably never max out everything at the same time, RapidIO seems good enough to me. I'm not going to wait for the G6
post #53 of 357
[quote]Originally posted by THT:
<strong>LOTS OF INTERESTING STUFF</strong><hr></blockquote>(but I won't waste form space; scroll up if you want to see it)

Thanks for the info I'm not as knowledgeable on this stuff as I used to be (obviously) <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />

One more thing (since you seem to know a lot about HT) it's busses can go beyond 16 bit, right?
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post #54 of 357
[quote]Originally posted by imacman287:
<strong>Dorsal's specs look like <a href="http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC8540&nodeId=02M0ylfVS0lM9 43030450467M98655" target="_blank">this.</a></strong><hr></blockquote>
And why should't they? <img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
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post #55 of 357
[quote]Originally posted by wfzelle:
<strong>What you might need at maximum:

- 1GB/s AGP
- 4*215GB/s 64-bit PCI = 860MB/s
- 100MB/s Firewire2
- 60MB/s USB 2

Total = 2020MB/s

</strong><hr></blockquote>

* bandwidth is not transferrate
* there's only one PCI bus with 4 Slots
* a PowerMac has 2 USB busses


- 1GB/s AGP 4x
- 266MB/s 64-bit/33MHz PCI
- 100MB/s Firewire2
- 120MB/s USB 2
Total = 1.5 GB/s
post #56 of 357
I do know what the difference between a bit and a byte...sorry my B looked like a b

Peace,
G
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post #57 of 357
Basically a byte is 8 bits. So when you see something like 400Mb per second, divide by 8 and you get the byte translation: 50MB per second.
post #58 of 357
Eugene-----&gt; i don't think anyone has picked up on your collusive hidden message hahaha

we like bold letters haha
post #59 of 357
[quote]Originally posted by HOS:
<strong>In current designs (CPU on daughterboard, RAM on motherboard), there's one big bus which connects the CPU to the RAM to the AGP/PCI, which is shared amongst them.

In the design above (RAM on daughterboard), now our one big bus only has to connect daughterboard to AGP/PCI (plus secondary busses like IDE/Firewire/USB, etc).</strong><hr></blockquote>

I might be mistaken, but I think I just realized why Apple is crowing about DDR-SDRAM L3 cache in the current PowerMacs: in the next motherboard design, main RAM is going to be the L3 cache! It'll be on the daughtercard with its own pipe to the processor.

In other words, the CPU is already there, and the motherboard is catching up!

[edit: This also explains why Apple is taking so long to implement DDR: They're implementing a design that I don't think has occurred to anyone else - certainly not anyone in the personal computer industry.]

[ 03-20-2002: Message edited by: Amorph ]</p>
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post #60 of 357
[quote]Originally posted by Amorph:
<strong>

I might be mistaken, but I think I just realized why Apple is crowing about DDR-SDRAM L3 cache in the current PowerMacs: in the next motherboard design, main RAM is going to be the L3 cache! It'll be on the daughtercard with its own pipe to the processor.

In other words, the CPU is already there, and the motherboard is catching up!

[edit: This also explains why Apple is taking so long to implement DDR: They're implementing a design that I don't think has occurred to anyone else - certainly not anyone in the personal computer industry.]

[ 03-20-2002: Message edited by: Amorph ]</strong><hr></blockquote>
I think you are a little too enthousiastic, Amorph, the L3 Cache of the 7455 is limited to 2 MB, very far from what you can have with 3 DDRAM slots.
post #61 of 357
[quote]Originally posted by powerdoc:
<strong>
I think you are a little too enthousiastic, Amorph, the L3 Cache of the 7455 is limited to 2 MB, very far from what you can have with 3 DDRAM slots.</strong><hr></blockquote>

OK, so maybe the memory controller needs a bump. Still, the architecture is there, it seems to me.
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post #62 of 357
Thread Starter 
Hi. I'll try and answer some questions. it's not often I get to come back and talk some more so soon. Firstly, I cannot give you a concrete schedule on Apple's release dates. In the next month or so, is too soon but this summer is a likely release date. Unless you work for Apple you really don't have this knowledge (unless you work for an OEM graphics company like ATI or NVIDIA).

The case. As I stated we received the hardware in a G4 case. It is silver and light grey and it contains an equal amount of drive bays. But this is a common practice when releasing such hardware. Sometimes we get then in bare metal boxes that are nothing more than cheap PC cases with no front bezel. And late in development we might get a case that will resemble the finished case very closely.

PCI slots. They look like the slots in the G4 PowerMacs. This is also a PCI-X standard slot.

Firewire ports remain at 2 and are the same as the ones used in a IEEE1394a implimentation. Firewire comes in many different flavors. Apple's modern machines support 100, 200, and 400Mbps speeds while the new implimentation can scale to 1600Mbps over shielded copper. For faster than 1600Mb speeds you will need to transfer over fiber. This is not a design aspect for these machines however. But running a 400MBps device on a 1600Mbps Firewire bus will not result in faster performance. Firewire to IDE bridge chips will need to be redesigned to take advantage. But at 200MBps, even ATA/100 will be hard pressed to max out IEEE1394b.
post #63 of 357
[quote]Originally posted by Dorsal M:
<strong>Unless you work for Apple you really don't have this knowledge (unless you work for an OEM graphics company like ATI or NVIDIA).</strong><hr></blockquote>

By telling us all these things don't you worry that either ATI or Nvidia will lose alot of money when steve finds out about someone possibiliy from those company leaked some info about the next powermac ?
post #64 of 357
I have some information for you.

test 3 rack-mount PPC boxes. sealed. but inside contains some monitoring hardware. Can set/simulate RAM size, manipulate bus and CPU speed, measure temp and power drain.

2 boxes have same graphics, 1 has different. All use DDR. max 1-2GB. CPU heat and power is very very low. benchmark is close to 867-933 G4 on low machine, much faster on top. Can set PPC speed ~60% more than bottom machine. USB is 1.1 spec. One machine use 1Gb ethernet, others don't use. AGP is same speed all machines. One machine test with 4200rpm HDD, other 2 test only with 5400.

Firewire speed is faster setting for 2 and 4 times now using firewire. One machine use 2 firewire, other machine use one only. People says we have slow machine only test, very very fast machine no people can use, very hot, but many extra for PCI, RAM, and CPU.
post #65 of 357
[quote]Originally posted by Outsider:
<strong>...They took 7500 off the roadmap. To me this either means the G5 used by Apple will indeed be a 85XX or that the 7500 (the original name) will be an Apple specific part number that will not be available for outside buyers. Therefore no reason to include it on a roadmap.</strong><hr></blockquote>

Ha Ha Ha!
What kind of logic is that? No need to even mention something on roadmaps, since apple is the client. Apple can wait. They used to do that.
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post #66 of 357
Hmmm... Dorsal is back so soon. Interesting...

<img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" />
post #67 of 357
Amorph-

Remember that on Moto's roadmap, the G5/85xx gets an integrated DDR controller, so adopting "local" DDR SDRAM (in place of L3 cache as you point out) really isn't out of line at all.

Plus, what gets more interesting is, how will Apple implement multiple processors in this situation?

On other boards (which will remain nameless for the moment), there's been some speculation about going to a MP design where you'll have (say) multiple daughterboards, each daughterboard with its own DDR . The connection between daughterboard is via RapidIO (a nice switched bus- why make the bus switched if you're never going to need it?). Then the question is, now that you've got loosely coupled CPUs, what sort of a model do you present?

More speculation on this led to a non-uniform memory access model, where each CPU has local memory, but all memory is addressable by all CPUs- it's just that the latency out to non-local memory is higher.

This should avoid wierd cache coherency schemes since all memory is addressable to all CPUs- no need to reserve some memory per CPU.

Interesting, no?

-HOS
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post #68 of 357
Ah hmm, what's the processor speed Dorsal?
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post #69 of 357
[quote]Originally posted by HOS:
<strong>Amorph-

Remember that on Moto's roadmap, the G5/85xx gets an integrated DDR controller, so adopting "local" DDR SDRAM (in place of L3 cache as you point out) really isn't out of line at all.

Plus, what gets more interesting is, how will Apple implement multiple processors in this situation?

On other boards (which will remain nameless for the moment), there's been some speculation about going to a MP design where you'll have (say) multiple daughterboards, each daughterboard with its own DDR . The connection between daughterboard is via RapidIO (a nice switched bus- why make the bus switched if you're never going to need it?). Then the question is, now that you've got loosely coupled CPUs, what sort of a model do you present?</strong><hr></blockquote>

Well, NeXTStep had some pretty buff clustering capabilities as I recall, and the whole point of clustering is that multiple machines act like one big machine from the point of view of the software...

This is all very interesting.
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post #70 of 357
post #71 of 357
[quote]Originally posted by murk:
<strong>Yeah! Dorsal's back! Can Kormac be far behind? </strong><hr></blockquote>



Let that last keynote serve as yet another pin through the eye of that great mass of ignorant believers out there. We were all supposed to be using pocketable super-computers nearly 2 years ago. At this rate Apple will be lucky if it can supply half the performance of a PocketPC in a package 10 times the size and 5 times the price. Soon PalmOS geeks will be gloating about how their palms out-perform Powermacs in 3-D.

But don't worry, I'm sure Stevie-boy will make it all better with a nice farcical price increase.
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post #72 of 357
I'm sorry Matsu, but that's the dumbest post I think I've ever read.
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post #73 of 357
LOL.

Now that the iMac is priced to compete head to head with high-end 'Nix workstations, the market share is going to fall into Apple's domain like a landslide.

post #74 of 357
[quote]Originally posted by Tarbash:
<strong>I'm sorry Matsu, but that's the dumbest post I think I've ever read.</strong><hr></blockquote>

I'm not too sure, he's got hot competition from a host of other morons on this forum (no names... yet).

However, the most recent Matsu dribble is quite worthy of Most Moronic Post, I really can't decide. Choices, choices
post #75 of 357
ok folks,here is my updated take on the g5.
i believe that what were are going to get at macworld newyork IS the real G5!
i think it exist and is ready to go.
i dont think the 7500 is the G5 but a super-G4!
it has a lot of the capabilities of the g4 but it wont be able to keep up with the G5.
i dont even think the 7500 exist yet,but i think the 8500 does.
anyone who doubts apple will be humbled come the next macworld!
i still dont think we will see an all-new motherboard with the initial iteration of the G5 power-mac.
but i think the next macworld san francisco will see an all-new motherboard.
im drooling over the prospect of a aqua-enhanching graphics subsystem and optical port.
i dont think in terms of MIPS or wheatstones or whatever,i think in terms of apps,new ways of working,ect....
and so does apple.
post #76 of 357
I think the sky is falling.
post #77 of 357
I am still here.

Well. Things begin to happen. I am glad to see it.

Next step will be at NAB at Apr 8th.

Let me ask a question!

Why Apple choose 23inch TFT-LCD Monitor as Cinma HD ?

it does not have any input for HDTV reception.

Or will it be ?

It came from LG.Philips LCD Co., Ltd as OEM part.

<a href="http://www.lgphilips-lcd.com:8888/English/product/p.html" target="_blank">http://www.lgphilips-lcd.com:8888/English/product/p.html</a>

It is in the montor section.

23" Wide UXGA LM230W1
Feature
-Wide Type
-High Resolution(UXGA)
-Wide Viewing Angle(Super-IPS)


Model Name LM230W1
Active Area[mm] 470.4 x 301.1
Outline Dimension[mm] 550.0 x 362.5
Thickness[mm] 24
Resolution 1920xRGBx1200
Aspect Ratio 16:10
Pixel Pitch[mm] 0.258(98.4)
Number of Colors 16.7M
Luminance[cd/㎡] 235cd/㎡,6lamps
Color Saturation 65
Weight[g] 5,500
Contrast Ratio 300 : 1
Interface TMDS
Viewing Angel[˚,U/D/L/R] 80/80/80/80(Super-IPS)
Color Temperature[K] 6,500
Response Time[ms] 40
MP Schedule Now

23" Wide UXGA LM230W1

What will be next ?

<a href="http://www.lgphilips-lcd.com:8888/English/news/n_cozy.html?idx=401&offset=0&pkinds=movement&pname =news" target="_blank">http://www.lgphilips-lcd.com:8888/English/news/n_cozy.html?idx=401&offset=0&pkinds=movement&pname =news</a>

or

<a href="http://www.samsungelectronics.com/semiconductors/TFT_LCD/product_news/semiadmin_1010104542921_108.html" target="_blank">http://www.samsungelectronics.com/semiconductors/TFT_LCD/product_news/semiadmin_1010104542921_108.html</a>

And if you can remember what I was talked about, I think we will see good sign soon.

P.S.: SAMSUNG & LG.Philips LCD Co., Ltd is making TFT-LCD for New iMac.

[ 03-21-2002: Message edited by: kormac77 ]</p>
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post #78 of 357
Yikes!

Suddenly, the "There is no G5 Theory" espoused by y/t looks a little thin.....

Might lose this bet after all.

SdC, SdA, and CMC (Color Me Concerned), aka:

There is no G5

[ 03-21-2002: Message edited by: There is no g5 ]</p>
Suckfuldotwhatever, dude.

It's the FSB, not the proc speed that is the problem. Your fire engine isn't worth sh:t no matter how big the pump is if it uses a garden hose to put out fires. Let's at...
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Suckfuldotwhatever, dude.

It's the FSB, not the proc speed that is the problem. Your fire engine isn't worth sh:t no matter how big the pump is if it uses a garden hose to put out fires. Let's at...
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post #79 of 357
[quote]Originally posted by kormac77:
<strong>And if you can remember what I was talked about, I think we will see good sign soon.</strong><hr></blockquote>

Honestly I don't remember except something about DNA you talked about since like 1999. But since 2001 Apple already changed the strategy from a computer maker to consumer electronics maker, so I am not sure if those things you said in 1999 still holds even you got inside info at 1999.

But I do believe that G5 will be coming before the end of 2002.
post #80 of 357
Alright K-Man!

Good to see you back old sod. Keep on giving us the inside scoop.

Finally!

<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" />
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