<strong>Originally posted by MaCommentary:
1) Wasn't there a rumor going around that Apple would call the 7500 the G5 even though it's really just a G4 with some G5 features? I mean remember that the original G4 was a G3 with an altivec unit on it.</strong>
The original Motorola roadmap had the G5 as a 7500 processor. It's only last Fall that Moto changed the roadmap to the current and confusing one. Previsouly, Moto's embedded processors had numbers of 8xxx and G4 processors had numbers of 74xx. All that has been shot to hell now. What I'm saying is that the marketing numbers are irrelevant.
<strong>2) One interesting thing about Dorsal's post was the RapidIO running @ 500MHz. To my knowlegde, the HyperTransport consortium has only gone public with speeds up to 400 MHz. Apple is one of it's strongest players though, and I wouldn't be supprised if they had internal tests going on with higher speed RapidIO.</strong>
Both HT and RapidIO have to scale to 1 GHz clock rates to achieve superior bandwidth. The 500 MHz number is logical if not necessary. Considering that RapidIO, the 16 bit wide version, delivers 4 bytes per clock and at 500 MHz only delivers 2 GByte/s, that's barely enough to support main memory. No wonder there is a memory controller on the CPU die.
<strong>3) I may have heard wrong, but when your memory goes at 333MHz or 400MHz that L3 cache is really not needed.</strong>
You heard wrong. Now, cost could be a completely different issue. Ie, L3 cache won't gain you that much for the cost, so it won't be necessary from that standpoint, but main memory technologies won't be catching up to processor performance in the near future and a multi-cache design has its benefits.
1) Wasn't there a rumor going around that Apple would call the 7500 the G5 even though it's really just a G4 with some G5 features? I mean remember that the original G4 was a G3 with an altivec unit on it.</strong>
The original Motorola roadmap had the G5 as a 7500 processor. It's only last Fall that Moto changed the roadmap to the current and confusing one. Previsouly, Moto's embedded processors had numbers of 8xxx and G4 processors had numbers of 74xx. All that has been shot to hell now. What I'm saying is that the marketing numbers are irrelevant.
<strong>2) One interesting thing about Dorsal's post was the RapidIO running @ 500MHz. To my knowlegde, the HyperTransport consortium has only gone public with speeds up to 400 MHz. Apple is one of it's strongest players though, and I wouldn't be supprised if they had internal tests going on with higher speed RapidIO.</strong>
Both HT and RapidIO have to scale to 1 GHz clock rates to achieve superior bandwidth. The 500 MHz number is logical if not necessary. Considering that RapidIO, the 16 bit wide version, delivers 4 bytes per clock and at 500 MHz only delivers 2 GByte/s, that's barely enough to support main memory. No wonder there is a memory controller on the CPU die.
<strong>3) I may have heard wrong, but when your memory goes at 333MHz or 400MHz that L3 cache is really not needed.</strong>
You heard wrong. Now, cost could be a completely different issue. Ie, L3 cache won't gain you that much for the cost, so it won't be necessary from that standpoint, but main memory technologies won't be catching up to processor performance in the near future and a multi-cache design has its benefits.
Still, the architecture is there, it seems to me.
