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CONFIRMED: G5 enters volume production! - Page 4

post #121 of 240
[quote]Originally posted by Big Mac:
<strong>
"after eating pie, more voluminous than a dolphin..."

More voluminous than a dolphin. Dolphin is the codename for the G3 processor inside of the GameCube, which features SIMD instructions. After eating pie, of great volume, greater than that of Dolphin. </strong><hr></blockquote>

PI = processing instructions?
Apple PI = Altivec?

My interpretation: the G3 gets Altivec

In some other thread two people mentioned that Apple refused Motorola's G5 on that PI thing.

Both combined could mean that IBM's G3 gets more than the current Altivec. Either an enhanced Altivec or Altivec and other new instructions.

But this chip sound like an interim solution till a POWER-derived chip is ready.
post #122 of 240
[quote]Originally posted by johnsonwax:
<strong>What Apple needs to do is to *not* show incremental improvements now (they work better in a growing market when people will buy simply because they have budget), but rather to save them up and launch them all together when they can demonstrate an overall superior product.</strong><hr></blockquote>

Yeah, and most likely risk a few customers who need a machine now and say "hey, if apple isn't introducing nothing new now, then they wont later as well". That "save up performance for later" doesn't really work in computer markets.

[quote]Originally posted by johnsonwax:
<strong>Consider the creeping CPU speeds at Intel and AMD. How many people can articulate the benefits of 2.2 GHz over 1.6GHz? or 533MHz FSB vs. 333MHz? Oh, it's faster, sure, but faster enough to argue for funds to buy? How much faster? How much will we save with faster hardware? Those are the kinds of questions that come out when the money isn't there.</strong><hr></blockquote>

Most of those discussion I had the joy of listening too ended with "faster enough to save even more time". That's why former SGI shops are switching to PCs for 3D work.

[quote]Originally posted by johnsonwax:
<strong>A is 33% faster than B which is 33% faster than C which is 33% faster than D which is 33% faster than E. It doesn't sell as well in this market as if you said A is 400% faster than E. That requires that B-D never exist.

Keep in mind that Apple cannot grow market share by appeasing us. It does need to do that, but their user base is loyal and willing to be abused. They grow by converting, and people don't convert for marginal reasons.</strong><hr></blockquote>

But they are more likely to convert for marginal reasons than for no reasons at all. If someone considers converting _today_ and there were no 33% increases for the last 6 months he wont convert but buy another PC/Sun/SGI which means that he's done for 2 years. No converting here. And even if Apple has a 400% jump in 2 months it risks of beine even in two years time when it's upgrade time again.

[quote]Originally posted by johnsonwax:
<strong>From my view, Apple shouldn't sweat the incremental improvements. They should focus on demonstrating a substantial benefit to those outside of the current user base.</strong><hr></blockquote>

I am not saying you are completely wrong, just that incremental upgrades are nice too.
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post #123 of 240
[quote]Trinity is the code name for the Cube.<hr></blockquote>
I think you guys are too quick to accept this as the meaning of Trinity. I think it's clear. It refers to AIM.
post #124 of 240
Just a few comments:

- I heard about further instructions to be added to the PPC instruction set some time ago, those instructions were neither BookE compliant nor part of IBM Fast Path. Maybe they're what we call Apple PI here - as far as I remember those instructions were ment to precode information for the pipeline, similar to some VLIW designs. This could be it if "PI" means "pipeline instructions".

- I already told you that I have some Motorola G5 inside info, and I even posted some of it. I'm really surprised that Apple is said to have "killed" the Motorola G5, as I find the specs pretty amazing. As far as I can say the Motorola desktop G5 should be 50 to 100% faster than the G4, and it should have shipped in 2002 or in early 2003. If Apple has killed the Motorola G5 there must have been good reasons to do so, and there must be some kind of replacement. I don't think Apple will be able to stay with the G4 until 2004, when the Power5 will ship.

- Just for your information, although maybe not relevant: "Trinity" was in fact the Cube codename, while "Trident" was the PowerPC 620, basically a 64 bit version of the PPC604.

- I'm trying to get some inside info about future IBM PPC designs, I'll be back as soon as I know more...
post #125 of 240
[quote]Originally posted by haderach:
<strong>Just a few comments:

- I heard about further instructions to be added to the PPC instruction set some time ago, those instructions were neither BookE compliant nor part of IBM Fast Path. Maybe they're what we call Apple PI here - as far as I remember those instructions were ment to precode information for the pipeline, similar to some VLIW designs. This could be it if "PI" means "pipeline instructions".

- I already told you that I have some Motorola G5 inside info, and I even posted some of it. I'm really surprised that Apple is said to have "killed" the Motorola G5, as I find the specs pretty amazing. As far as I can say the Motorola desktop G5 should be 50 to 100% faster than the G4, and it should have shipped in 2002 or in early 2003. If Apple has killed the Motorola G5 there must have been good reasons to do so, and there must be some kind of replacement. I don't think Apple will be able to stay with the G4 until 2004, when the Power5 will ship.

- Just for your information, although maybe not relevant: "Trinity" was in fact the Cube codename, while "Trident" was the PowerPC 620, basically a 64 bit version of the PPC604.

- I'm trying to get some inside info about future IBM PPC designs, I'll be back as soon as I know more...</strong><hr></blockquote>

Here's your inside info on IBM PPC designs:

IBM has developed Power4. For the workstation.

On the low-end is a 1 chip, dual core design. High-end is a 1 chip, quad core... Shipping 4th quarter, 2002.

No word on any relation to these proc's and Apple. However, if this chip begins shipping in Q4, that would mean Sept., which would work out well if new Power Macs utilizing this chip were intro'd during MWNY... :cool:
post #126 of 240
[quote]Originally posted by justafriend:
<strong>

Here's your inside info on IBM PPC designs:

IBM has developed Power4. For the workstation.

On the low-end is a 1 chip, dual core design. High-end is a 1 chip, quad core... Shipping 4th quarter, 2002.

No word on any relation to these proc's and Apple. However, if this chip begins shipping in Q4, that would mean Sept., which would work out well if new Power Macs utilizing this chip were intro'd during MWNY... :cool: </strong><hr></blockquote>

Uh, that's not inside info -- that's public knowledge because the Q4 in question was last year. The POWER4 has been out since Oct 2001.

I don't think Motorola would balk at adding AltiVec, and Apple already has its own name for it (VelocityEngine) so they wouldn't call it Pi. Pipeline instructions is a good name, but it doesn't tell me what it means.
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post #127 of 240
[quote]Originally posted by Programmer:
<strong>

Uh, that's not inside info -- that's public knowledge because the Q4 in question was last year. The POWER4 has been out since Oct 2001.

I don't think Motorola would balk at adding AltiVec, and Apple already has its own name for it (VelocityEngine) so they wouldn't call it Pi. Pipeline instructions is a good name, but it doesn't tell me what it means.</strong><hr></blockquote>

For clarification purposes, what's been out since last year is the SERVER version. This is a WORKSTATION version - a derivative of the server chip... (this isn't out yet ;o)

[ 06-12-2002: Message edited by: justafriend ]</p>
post #128 of 240
[quote]Originally posted by MrSparkle:
<strong>I think you guys are too quick to accept this as the meaning of Trinity. I think it's clear. It refers to AIM.</strong><hr></blockquote>

This looks like fun.

Pi fits nicely with Pipeline Instructions.
Trinity makes the most sense as a reference to AIM, which means IBM is back in the game.
Dolphin is a tough one -- that IC company just doesn't look like something relevant, or at least their publicly announced products don't. Dolphin was the code name for the whole GameCube, not the processor in it.
IBM's G3 is just not a suitable replacement for Motorola's G4, even with SIMD added -- MPX bus might only be 166 MHz, but it is more efficient than the G3's 60x bus; the G4's FPU is faster; the G4 7455 has more functional units and longer pipes, allowing higher clock rates; the G4 has wider internal busses and better caches; etc. IBM would have to push the G3 a long way to catch up. More likely would be either buying the G4 from Motorola (probably not), or starting from a new design (not in the near term).

The GameCube's Gekko chip doesn't have "awesome memory bandwidth" as somebody said above... it is just a slightly more efficient G3, limited to the 60x bus @ 100 MHz (IIRC). The system has really good memory bandwidth, and most of it is used by the graphics chip without disturbing the processor's access to memory. Rather like the Xserve in that sense. There are a couple of processor extensions, but AltiVec provides equivalent or better capabilities already.

So I think "Dolphin" is probably a reference to a large cube-like Mac design. We know Steve likes his cubes.
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post #129 of 240
[quote]Originally posted by justafriend:
<strong>
For clarification purposes, what's been out since last year is the SERVER version. This is a WORKSTATION version - a derivative of the server chip... (this isn't out yet ;o)
</strong><hr></blockquote>

Aha, thank you. Is there any public reference to this at all, or is it really insider info?
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post #130 of 240
If, by "after eating pie" references to "Pi" the number it to means that a nice improvement in floating point arithmetic will come around the corner. Which is good for workstation work.
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post #131 of 240
[quote]Originally posted by stw:
<strong>My interpretation: the G3 gets Altivec</strong><hr></blockquote>

Isn't that a G4?
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post #132 of 240
[quote]Originally posted by Programmer:
<strong>

Aha, thank you. Is there any public reference to this at all, or is it really insider info?</strong><hr></blockquote>

Unfortunately, no direct public reference. I posed a question to my acquantance in IBM, and was told that the answer to the specific question I asked was "IBM Confidential". Then, it was followed by, "but what I can tell you..." and that's what I posted here.

As an aside, Jamee Abdulhafiz is listed on this page ( <a href="http://www.research.ibm.com/journal/rd/461/luddeaut.html" target="_blank">http://www.research.ibm.com/journal/rd/461/luddeaut.html</a> ) as Senior Engineer and verification leader for a POWER4 derivative microprocessor...

So, there is some proof to the statement that Power4 derivatives are planned... Just no detail like what I was provided.

[ 06-12-2002: Message edited by: justafriend ]</p>
post #133 of 240
[quote](512KB L2 cache/4MB L3 cache per CPU), 400MHz FSB, 2GB PC2600 DDR SDRAM<hr></blockquote>

L3 cache is unlikely with high speed RAM, as it offer less of a performance advantage. It may just vbe tiding the G4+ over until a faster FSB along.

[quote]If I recall correctly "Pi" meant Pipeline Instructions. Apple PI was some sort of custom pipeline instructions that Apple wanted in the G5 chip<hr></blockquote>

Aren't pipelines (currently) invisible to code executing on them? Any examples of what a pipeline instruction would do with the pipeline?

[quote]Trinity makes the most sense as a reference to AIM, which means IBM is back in the game.<hr></blockquote>

At first I thought AOL == AOL Instant Messenger <img src="graemlins/embarrassed.gif" border="0" alt="[Embarrassed]" />

[quote]The GameCube's Gekko chip doesn't have "awesome memory bandwidth" as somebody said above... it is just a slightly more efficient G3, limited to the 60x bus @ 100 MHz (IIRC). <hr></blockquote>

From Nintendo's pages:
External Bus 1.3GB/second peak bandwidth (32-bit address space, 64-bit data bus 162 MHz clock)

Not awesome but better than 60x.

[ 06-12-2002: Message edited by: Stoo ]</p>
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post #134 of 240
[quote]Originally posted by Programmer:
<strong>

The GameCube's Gekko chip doesn't have "awesome memory bandwidth" as somebody said above... it is just a slightly more efficient G3, limited to the 60x bus @ 100 MHz (IIRC.</strong><hr></blockquote>

Stoo is right, it runs at 162 Mhz. What's more interesting though is that IBM says it supports some sort of data compression, like the recent graphics chips, that results in an "effective" 5.2 GB/s.
post #135 of 240
I'm wondering if anyone can help out here with links. I can't seem to find much information on the Power4 on IBM's site. An index posted on has a link to PPC - Power is MIA. And when I use their search engine, the best I can find are press releases praising the Power4.

I need more information! Additionally, can anyone else confirm that Power5 and Power6 chips are being developed?

[ 06-12-2002: Message edited by: Big Mac ]</p>
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post #136 of 240
[quote]Originally posted by Big Mac:
<strong>I'm wondering if anyone can help out here with links. I can't seem to find much information on the Power4 on IBM's site. An index posted on has a link to PPC - Power is MIA. And when I use their search engine, the best I can find are press releases praising the Power4.
</strong><hr></blockquote>

Here's the <a href="http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power4.html" target="_blank">white paper</a> on the Power4.
post #137 of 240
[quote]Originally posted by timortis:
<strong>Stoo is right, it runs at 162 Mhz. What's more interesting though is that IBM says it supports some sort of data compression, like the recent graphics chips, that results in an "effective" 5.2 GB/s.</strong><hr></blockquote>

Hmmm... you might be right about the clock rate. It is a modified 60x bus protocol, however, and doesn't sustain that peak throughput for very long (i.e. one cacheline burst at a time). The supposed "data compression" is simply fixed &lt;-&gt; float conversions in hardware together with a write combining write-thru pipe that was hacked onto the chip and has numerous issues, plus it must be explicitly coded for by the software developers. Very useful, to be sure, but it wouldn't be suited as-is in a Mac... besides which AltiVec can already do the fixed/float conversions better, and has cache streaming instructions and a higher clock rate.

The Apple Pi instructions could certainly be yet more improvements to the AltiVec cache controls -- that would be cool, but FSB bus speeds would need to increase to really make the most of it.


Oh -- one more thing about the GameCube... what I meant originally was that its memory is capable of more bandwidth than the processor can use. This is why the graphics engine running at full speed doesn't get in the way of the Gekkco. Hence the similar nature to the Xserve.

[ 06-12-2002: Message edited by: Programmer ]</p>
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post #138 of 240
I seem to recall that Gastermating (the arch-rival of Mastergating) predicted the "Pi-Mac" months ago. MWSF 02 I think. So hey, maybe he was onto something. Maybe the next generation of Power Macs really will run at 3.14 GHz, boosted by the new Pipeline Instructions!

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post #139 of 240
Kudos must go to Junkyard Dawg for starting a 4, FOUR, page thread with a rumor dated November 2001.

Unbelievable. That's why I like Appleinsider fo much. :eek:
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post #140 of 240
Thread Starter 
No, the credit goes to all the others here with real technical knowledge. This is a very interesting thread because of them, and I'm really diggin' the info/speculation about IBM and the G5.
post #141 of 240
Amorph said:

[quote]Trinity is the code name for the Cube. <hr></blockquote>

I thought that Trinity was the name of the lead female character in "The Matrix." So, hopefully we'll be getting an Altivec-enhanced Matrix screensaver from Apple at MWNY '02.
post #142 of 240
[quote]Originally posted by Amorph:
<strong>

That would work for me. As nifty as a dedicated DSP on the memory controller might be in theory, it has a good chance of getting orphaned, like the DSP in the old AV series. Or IBM's ill-starred MicroChannel architecture.

[ 06-11-2002: Message edited by: Amorph ]</strong><hr></blockquote>

I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.
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post #143 of 240
[quote]Originally posted by moki:
<strong>

I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.</strong><hr></blockquote>

Ah, so we are going to be disappointed again? So you think it will be MWSF before anything really juicy comes? I'm eager to ebay my dual gig when the next big thing comes out, but not for a gapper upgrade.
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post #144 of 240
[quote]Originally posted by moki:
<strong>

I'm going to have to take that back a bit -- the mobo I mentioned has apparently slipped again, due to the reasons I mentioned earlier. What will be at MacWorld will most likely NOT be the DDR implementation I mentioned, but rather, a less ambitious one.</strong><hr></blockquote>

Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.

D
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post #145 of 240
[quote]Originally posted by DoughBoy:
<strong>Amorph said:
I thought that Trinity was the name of the lead female character in "The Matrix." So, hopefully we'll be getting an Altivec-enhanced Matrix screensaver from Apple at MWNY '02. </strong><hr></blockquote>


Sorry, but it's been "conformed" that this screensaveer has been postponed until MWSF '03.
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post #146 of 240
"A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin..."

The Greek god Apollo sometimes appeared as a Dolphin in order to "navigate people to his oracle".

dolphin = G4 Apollo(?)

AIM hasn't really gone away, so how can it return? The Cube has gone away but:

Cube ? returns after Pipeline Instructions, more voluminous than a G4 Apollo.

I could see an easy prediction for faster FSB implementation for Apollo's successor (G5 or G4), and in a new case (Cube), but my gut feeling is that, (assuming there is a valid rumor here) it would be more of a revelation than this.
post #147 of 240
[quote]Originally posted by DoughBoy:
<strong>I thought that Trinity was the name of the lead female character in "The Matrix." So, hopefully we'll be getting an Altivec-enhanced Matrix screensaver from Apple at MWNY '02. </strong><hr></blockquote>

Trinity was also the codename for the QuakeIII engine developed by iD software.
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post #148 of 240
[quote]Originally posted by DaveGee:
<strong>
Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.
</strong><hr></blockquote>

Apple Computer confirmed today that CEO Steve Jobs will deliver his July keynote address from behind a 3" shield of bulletproof plexiglass, from which he is expected to announce upgrades to Apple's hardware, including its line of professional systems. A company spokesperson said only that the company has "credible information" about a possible threat to Jobs' life. Apple's online user community was quick to react, dubbing the new safety measure the "iShield" and "RDF 2.0."

In an unrelated story, today Apple also unveiled its latest marketing effort, "The Bandwidth Myth." Jobs is expected to explain this effort more fully in his keynote address.
post #149 of 240
I can imagine Schiller stashed in some bunker under Cupertino, kept separate from Jobs at all times, but videoconferencing* with the board members.

*Appropriately with Apple's new iCam app and device.

Screed

[ 06-12-2002: Message edited by: sCreeD ]</p>
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post #150 of 240
[quote]Originally posted by KidRed:
<strong>I read in February I think about 'looking to someone rather then MOTO for Apple's next chip". Basically saying IBM was going to do it. So there seems to be a lot of sharing of the same sentiment that IBM will be doing Apple's next chip.</strong><hr></blockquote>
yeah, i originally said that. i didn't realize i was using such cryptic language. but if you search for it i said that right around february or so.
post #151 of 240
[quote]Originally posted by DaveGee:
<strong>

Good grief... I sure hope this is just dis-info campain because If Steve takes the wraps of a brandy-new dual 1.01Ghz DP running at a 'wicked fast' 133Mhz bus and call it a day I think everyone will storm the stage.

D</strong><hr></blockquote>

What I meant was that the new mobo with things like USB 2, 800mbps FireWire, 4 on-controller DSPs, DDR, etc. is still hung up with production issues. It was supposed to be out about 8 months ago, but it still isn't ready.

So instead, there will be a less ambitious DDR motherboard, with speedbumped G4's I'd imagine. I realize it may seem like a small upgrade, but the reality is that a faster bus will make a rather substantial difference in performance for many operations.

People who are claiming that the DDR implementation in the Xserve isn't "real" aren't understanding the issues. The DDR implementation is full-on DDR from the memory controller to system memory. The processor bus is already way faster than system memory anyway, so the DDR implementation in the Xserve and also in the upcoming G4 towers does indeed make a performance difference.

I don't expect that the alliance with IBM, if there is one will bear fruit for another year or so. Until then, speed bumped G4's and better motherboards is likely what you'll see.
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post #152 of 240
[quote]Originally posted by DaveGee:
<strong>Getting back to Apple 3.1415 (pi) (pie) whatever...

Remember back pre-MWSF and we had those criptic messages from Codename?

Well here was one of his messages:

"A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin..."

No connection I'm sure but since some of the stuff that Codename posted is starting to come true 'Rosetta' for one it got me to thinking... and now a new reference to 'pie' when that was one item I never could find a connection to...

Oh well... as you were..

Dave</strong><hr></blockquote>
it was probably related. i heard the term pi used in reference to this right around then. and it was referred to in the past tense, so the info was already out there.
post #153 of 240
[quote]Originally posted by moki:
<strong>
People who are claiming that the DDR implementation in the Xserve isn't "real" aren't understanding the issues. The DDR implementation is full-on DDR from the memory controller to system memory. The processor bus is already way faster than system memory anyway, so the DDR implementation in the Xserve and also in the upcoming G4 towers does indeed make a performance difference.
</strong><hr></blockquote>

How is the current processor bus faster than DDR memory? It only runs at a SDR 133 Mhz, whereas PC 2100 DDR Memory is, well, DDR 133 Mhz. It provides twice the bandwidth than what the processor is capable of accessing because of its limited bus capacity.
post #154 of 240
[quote]<strong>
No connection I'm sure but since some of the stuff that Codename posted is starting to come true 'Rosetta' for one it got me to thinking... and now a new reference to 'pie' when that was one item I never could find a connection to...
</strong><hr></blockquote>

What exactly is/was 'Rosetta'?
post #155 of 240
[quote]Originally posted by timortis:
<strong>

How is the current processor bus faster than DDR memory? It only runs at a SDR 133 Mhz, whereas PC 2100 DDR Memory is, well, DDR 133 Mhz. It provides twice the bandwidth than what the processor is capable of accessing because of its limited bus capacity.</strong><hr></blockquote>

You're confusing the system bus with the processor bus.
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post #156 of 240
[quote]Originally posted by moki:
<strong>

You're confusing the system bus with the processor bus.</strong><hr></blockquote>

No, you're confusing them, unfortunately.
post #157 of 240
[quote]Originally posted by timortis:
<strong>

No, you're confusing them, unfortunately.</strong><hr></blockquote>



As shown above, they are two different things.

It is my understanding that the 133mhz processor bus, depicted above, is *not* limited to 133mhz (in future mobo's), and thus the use of DDR will indeed be quite fortunate.

If you have information to the contrary, I'd love to hear it...
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post #158 of 240
[quote]Originally posted by moki:
<strong>



As shown above, they are two different things.

It is my understanding that the 133mhz processor bus, depicted above, is *not* limited to 133mhz (in future mobo's), and thus the use of DDR will indeed be quite fortunate.

If you have information to the contrary, I'd love to hear it...</strong><hr></blockquote>

I am talking about the G4 systems that are currently available. Including the DDR Xserve. What you call "System Bus" cannot run at more than what the processor supports. In the case of current G4s, they support 100 and 133 Mhz 64 bit busses, single data rate.

If you're saying that you have positive information that future (MWNY?) motherboards will use a faster bus, this means they will use a different (new and improved) G4. Which is great news and what we've been hoping for.
post #159 of 240
[quote]Originally posted by timortis:
<strong>

I am talking about the G4 systems that are currently available. Including the DDR Xserve. What you call "System Bus" cannot run at more than what the processor supports. In the case of current G4s, they support 100 and 133 Mhz 64 bit busses, single data rate.

If you're saying that you have positive information that future (MWNY?) motherboards will use a faster bus, this means they will use a different (new and improved) G4. Which is great news and what we've been hoping for.</strong><hr></blockquote>

If I had *positive* news on anything, I'd be under NDA. However, my understanding is that the DDR support in the new mobo does a significant job in increasing bus bandwidth, and I fail to see how that is possible unless the Maxbus supports either high speeds or accessing on both the up and down cycle of the bus, ala DDR.

I do know that the current 7450 supports DDR access to L3 Cache RAM, perhaps it supports it via Maxbus (the processor bus) as well? I've been looking over the PDFs at MOT to see for sure:

<a href="http://search.motorola.com/semiconductors/query.html?qt=g4+maxbus" target="_blank">http://search.motorola.com/semiconductors/query.html?qt=g4+maxbus</a>

[quote]For superior cache performance and reliability, the
MPC7450 adds DDR SRAM support and address
parity on the L3 bus. The MPC750 interfaces only
to synchronous burst SRAMs or late-write SRAMs
on the L2 bus and does not support L2 address
parity.

.....

Note that an upgrade from the MPC750 at 100MHz
to a MPC74xx at 133MHz can produce a sustained
system bus bandwidth improvement of more than
3x.
<hr></blockquote>

This is all old information, of course.

[ 06-12-2002: Message edited by: moki ]</p>
Andrew Welch / el Presidente / Ambrosia Software, Inc.
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post #160 of 240
[quote]Originally posted by Big Mac:
<strong>I need more information! Additionally, can anyone else confirm that Power5 and Power6 chips are being developed?</strong><hr></blockquote>

Even if there is no posted information (though they have made comments to release schedules) I can tell you from an engineering point of view and the development times involved they are already in development. Just don't ask me what they are developing as I don't work for IBM, although I have a friend who does.
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