<strong>Originally posted by Programmer:
Well here are the "facts" that I'm aware of (plus one supposition), and I think they explain what everybody is saying even though the end result still isn't as happy as a G5 w/ on-chip memory controller....</strong>
Um, I used to think, 2 or 3 years ago, that on-chip memory controllers would be cool, but that was when I didn't understand the economics very well. Processor performance will always be way beyond memory performance (with semiconductors). So, any memory technology in the near future will never be able to provide the bandwidth for a modern CPU, and I think the magic should be in the cache design, but I digress.
The economics is that I don't think there is any need for anything more than a dual processor machine in the consumer space for one reason, Moore's Law. Next gen fab tech doubles the number of transistors that a consumer CPU can have thereby eliminating the need for anything more for dual processor machines, if that. In addition, I wonder at the efficacy of dual processors when compared to CMP and or SMT designs.
Since that is the case imo, a shared memory architecture should be able to compete with any on-die memory controller, and I don't think it is worth the effort to design a NUMA architecture for a market that really doesn't need it and is more expensive then a shared system to boot.
So a hypothetical PPC with monster backside cache (16 to 128 MByte at >8 GByte/s bandwidth) and a RapidIO/Hypertransport bus is fine with me.
<strong>Moto's head of PPC development has said that MPX will not
be significantly changed because the embedded customers are very happy with it and compatibility doesn't want to become an issue. A speed bump to 166 MHz is possible at some unspecified point in time. This means no DDR MPX, and maximum of 1.3 GB/sec.</strong>
I can't for the life of me think why DDR signalling for a MPX bus would be a significant change??? But I do think that economically and politically, Motorola seems to be getting out of the system ASIC business, is simply dragging its feet on DDR MPX, and is waiting for CPUs with on-die memory controllers to ship.
<strong>Current PowerMacs achieve ~800 MB/sec in practice under very optimized circumstances. This is about 80% efficiency, which is remarkable from SDRAM who's theoretical peak is ~1 GB/sec. Usually it is more like 700 MB/sec or so.</strong>
If this is true, the MPX bus already provides the memory bandwidth seen in x86 PC2100 DDR SDRAM systems. If it's true. Probably for random I/O, but for streaming reads, who knows.