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CONFIRMED: G5 enters volume production! - Page 3

post #81 of 240
[quote]Originally posted by timortis:
<strong>
[re: moki's idea of custom DSPs astride the memory controller]

Of course, apps would have to be coded to take advantage of this new hardware.</strong><hr></blockquote>

That depends on how Apple decides to implement them. If they understand a subset of the AltiVec instruction set, then Apple could probably include logic to reroute those instructions on the fly, and forward anything that they can't handle across the bus. It wouldn't be easy (and, to be honest, I'm not sure if it's even practicable) but it certainly would be transparent.
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post #82 of 240
[quote]Originally posted by Programmer:
<strong>

I'm curious about what the supposed "Apple Pi" extensions could be... HyperTransport, perhaps? More specialized graphics instructions for Quartz? Fancy DMA features for use with the on-chip memory controller? Hyper-threading? Steve's favourite recipe for apple pie?</strong><hr></blockquote>

... I suspect it's as much any one of those things, as it was a conveniently contrived excuse to run screaming from Moto as fast as possible.
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post #83 of 240
[quote]Originally posted by Amorph:
<strong>

That depends on how Apple decides to implement them. If they understand a subset of the AltiVec instruction set, then Apple could probably include logic to reroute those instructions on the fly, and forward anything that they can't handle across the bus. It wouldn't be easy (and, to be honest, I'm not sure if it's even practicable) but it certainly would be transparent.</strong><hr></blockquote>

No, it would need to be custom-coded -- and in reality, only a very few applications would likely end up using them. We're talking about very light-weight DSPs here. However, for certain very specific applications, they'll enabled some very cool stuff to happen.

[ 06-11-2002: Message edited by: moki ]</p>
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post #84 of 240
[quote]Originally posted by moki:
<strong>

What would seem mostly likely for the Pro line at MacWorld would be a DDR machine with USB 2, 800mbs FireWire, and a fairly nifty feature (which will be used only by a very few engineers): mini DSPs sitting on the memory controller, allowing things like MPEG4 to be done with close to zero overhead.
</strong><hr></blockquote>

Hmm. Given Apple's focus on owning the DV market outright, this would make sense. Makes me think that a mini-DSP would be labeled as Velocity Engine Pro, or some damn thing, clearing the way for Altivec to get tossed and possibly Moto along with it.

Apple should be in a position to take Altivec away from Mot (Apple really designed it, IIRC), and while IBM clearly could care less about putting it in their chips, nVidia might like to take a crack at putting it in their stuff. By breaking this apart, Apple would gain a lot of flexibility in their hardware path and would possibly get a new partner in nVidia.

Also by yanking out the Altivec, Apple can put more traditional chips into more traditional hardware (xServe doesn't need Altivec for many of it's markets) for less, and make some weirder stuff for the pro users that would really use it.

There really are only a few developers that use Altivec - mostly Adobe and Apple and some of the engineering apps (BLAST) but the stuff that would really benefit from this are pretty high-end, and therefore easier to get ported to new hardware.

All in all, sounds like a reasonable plan. It would also explain some of the odd G5 rumors. The G5 really could be done, but Apple could hardly ship an Altivec-lacking G5 box unless the dsp hardware and mobo were solid. After all, the PS bake-off against the G4 would backfire without the dsp support. It certainly makes it clearer why Apple would be buying up so many high-end DV apps and de-committing to other platforms. Apple could ensure that the new dsp stuff is built in to these apps, and why run a P4 version of the app if it's 1/5 the speed, so why ship it. Unlike some others, I don't think Apple is interested in shuttering itself out of the x86 market just for spite. I think if Apple drops a profitable x86 product, it'll be for good reason.

So the G5 could essentially be done, and if done by IBM, you certainly wouldn't see any evidence at Mots website. It would also explain any rumors that Apple killed the G5 (Mot's proposed version) It could really be ready for volume production. It could just be that Apple hasn't gotten the mobo and the developers in line to release it, and a bad rollout would give the chip a bad reputation, which Apple needs to avoid.

Ok, there's a lot of 'what if's' in there, but nothing that's too much of a stretch if Moki is hinting us the right way.
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post #85 of 240
[quote]Originally posted by moki:
<strong>
I am not under NDA for any of this stuff, and indeed, it is a mixture of water cooler talk and speculation. But still, you know people here and there, you can put the pieces together. Clearly there is no way in hell I'd state anything that could affect any NDAs with anyone.
</strong><hr></blockquote>

So, what did Apple say about a Java 1.4 timeframe at WWDC?

I need it badly!!!
post #86 of 240
[quote]Originally posted by johnsonwax:
<strong>All in all, sounds like a reasonable plan. It would also explain some of the odd G5 rumors. The G5 really could be done, but Apple could hardly ship an Altivec-lacking G5 box unless the dsp hardware and mobo were solid. After all, the PS bake-off against the G4 would backfire without the dsp support. It certainly makes it clearer why Apple would be buying up so many high-end DV apps and de-committing to other platforms. Apple could ensure that the new dsp stuff is built in to these apps, and why run a P4 version of the app if it's 1/5 the speed, so why ship it. Unlike some others, I don't think Apple is interested in shuttering itself out of the x86 market just for spite. I think if Apple drops a profitable x86 product, it'll be for good reason.
</strong><hr></blockquote>

While I don't know the details of exactly what these DSPs will be capable of, I do know that they are not even close to being on par with general-purpose DSPs or what AltiVec is capable of.

That isn't what they are there for -- the idea is that as long as you have a memory controller that has to sit between main memory and your processor, why not give it some smarts so it can apply various algorithms to data as it is being shuffled to and from the processor.

[ 06-11-2002: Message edited by: moki ]</p>
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post #87 of 240
[quote]Originally posted by Amorph:
<strong>That depends on how Apple decides to implement them. If they understand a subset of the AltiVec instruction set, then Apple could probably include logic to reroute those instructions on the fly, and forward anything that they can't handle across the bus. It wouldn't be easy (and, to be honest, I'm not sure if it's even practicable) but it certainly would be transparent.</strong><hr></blockquote>


It really seems that there is a widespread and major misconception about what AltiVec is and how it works. It is simply a set of registers and instructions in the processor in addition to the integer & floating point registers and instructions. The day of having a seperate floating point unit is long gone, and the same is true of having a seperate vector unit. They are just far too tightly coupled to do that, not to mention that your memory controller runs at 200-300 MHz.

Putting this functionality into the memory controller is just a desperate bid to get more out of the DDR without improving the G4's front side bus. It will not replace AltiVec, and AltiVec should not go away -- all other processors have vector units, and IBM is adding vector units. Even if most programmers don't directly write AltiVec code, they implicitly take advantage of it because large amounts of system code do use it (OpenGL, QuickTime, network stack, and even just the basic copy memory routine). Apple doesn't own (and didn't design) AltiVec, but they probably have the rights to allow IBM to build a new SIMD implementation which is compatible with it.

So Moki has clarified... he expects to see an Xserve-like machine with a few nifty improvements and a clock rate bump. Well I won't be surprised by this at all, and with Quartz Extreme it will be a significantly faster machine even if it doesn't benchmark that well.
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post #88 of 240
And nVidia will be onboard. My friend is a stockholder and says that ~September nVidia is coming out with something cool with Apple.

Guess we will see...exciting times these are...
post #89 of 240
[quote]Originally posted by Programmer:
<strong>It really seems that there is a widespread and major misconception about what AltiVec is and how it works. It is simply a set of registers and instructions in the processor in addition to the integer & floating point registers and instructions. The day of having a seperate floating point unit is long gone, and the same is true of having a seperate vector unit. They are just far too tightly coupled to do that, not to mention that your memory controller runs at 200-300 MHz.</strong><hr></blockquote>

Eh?

All I said was that if the controller had a few simple DSP instructions on board to do transformations on the data coming from memory, it might be possible to sniff out those instructions and divert them, if the DSPs understood a subset of AltiVec instruction set. Why a subset? Because they're not going to have the full capability of AltiVec, but if they recognize the same instructions, no custom instructions have to be generated, either by the programmer or by the compiler, and the additional hardware will be transparent.

I was not talking about moving AltiVec to the memory controller altogether. As you point out, that doesn't make any sense.

Of course, I was thinking out loud. One major disadvantage to my approach - again, assuming that it is practicable in the first place - is that it would not be easy to write code specifically to take advantage of the controller's DSP capabilities (you'd have to write your AltiVec code knowing the controller's instruction routing logic), and so they'd seldom be used at anything like peak efficiency.

More tellingly, the controller could not be intelligent enough to discern a situation where a block of instructions would be more efficiently executed entirely by the processor.

[quote]<strong>Putting this functionality into the memory controller is just a desperate bid to get more out of the DDR without improving the G4's front side bus.</strong><hr></blockquote>

Actually, what it reminds me of is IBM's Channel architecture, where the busses themselves could be programmed to perform instructions on the data sent across them. If it's desperate, then IBM is guilty of tremendous amounts of desperation in designing their high end architectures. It's understandable: Bandwidth is crucial. On a personal computer platform, it's at a premium.

[quote]<strong>It will not replace AltiVec, and AltiVec should not go away</strong><hr></blockquote>

Obviously not. AltiVec is capable of accelerating incredibly complex calculations, and by its design and placement this hypothetical DSP would be meant to perform (relatively) simple transformations on streaming data.

[quote]<strong>Apple doesn't own (and didn't design) AltiVec, but they probably have the rights to allow IBM to build a new SIMD implementation which is compatible with it.</strong><hr></blockquote>

Are you sure they didn't at least have a hand in its design? I've read that they had an important, and possibly central, role in developing the instruction set, and in pushing for an onboard vector unit in the first place. The implementation in silicon is obviously all Moto, however.

[quote]<strong>So Moki has clarified... he expects to see an Xserve-like machine with a few nifty improvements and a clock rate bump. Well I won't be surprised by this at all, and with Quartz Extreme it will be a significantly faster machine even if it doesn't benchmark that well.</strong><hr></blockquote>

That would work for me. As nifty as a dedicated DSP on the memory controller might be in theory, it has a good chance of getting orphaned, like the DSP in the old AV series. Or IBM's ill-starred MicroChannel architecture.

[ 06-11-2002: Message edited by: Amorph ]</p>
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post #90 of 240
[quote]Originally posted by Programmer:
<strong>
Even if most programmers don't directly write AltiVec code, they implicitly take advantage of it because large amounts of system code do use it (OpenGL, QuickTime, network stack, and even just the basic copy memory routine). </strong>

Right. Which is why a replacement for Altivec isn't totally out of the question. So long as Apple is able to replicate the performance boost in the system code, most (but not all) developers wouldn't care. The ones that would care are probably few enough in number that Apple can throw engineers at them to help with moving their code, and large enough that moving the code would make financial sense if the performance benefits were really there.

That said, based the above comments, it doesn't sound like the DSPs are there for that purpose. But I think if we had an IBM G5 with a different SIMD engine, it would be a manageable transition for Apple, all things considered.

<strong>Apple doesn't own (and didn't design) AltiVec, but they probably have the rights to allow IBM to build a new SIMD implementation which is compatible with it.
</strong>

Actually, I'm pretty sure most of Altivec's design was driven by Apple. That's not to say that Mot didn't have a hand in it as well and doesn't have a contract preventing Apple from taking it to other vendors - certainly Mot benefits from it in their other products, but I'm quite sure Apple had a substantial role in it's development. It only makes sense that they can take Altivec with them in some way. The problem with IBM seemed to have as much to do with the fact that Altivec didn't line up with IBMs plans for the G4 as it did with it being an Apple/Mot technology.
<hr></blockquote>
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post #91 of 240
[quote]That isn't what they are there for -- the idea is that as long as you have a memory controller that has to sit between main memory and your processor, why not give it some smarts so it can apply various algorithms to data as it is being shuffled to and from the processor.<hr></blockquote>

latency ?
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post #92 of 240
[quote]Originally posted by johnsonwax:
<strong>


All in all, sounds like a reasonable plan. It would also explain some of the odd G5 rumors.

So the G5 could essentially be done, and if done by IBM, you certainly wouldn't see any evidence at Mots website. It would also explain any rumors that Apple killed the G5 (Mot's proposed version) It could really be ready for volume production. It could just be that Apple hasn't gotten the mobo and the developers in line to release it, and a bad rollout would give the chip a bad reputation, which Apple needs to avoid.

Ok, there's a lot of 'what if's' in there, but nothing that's too much of a stretch if Moki is hinting us the right way.</strong><hr></blockquote>

Also, add the fact that MOTO removed the G5 from it's road map. Maybe that explains why. Also, IBM announced along with the Sahara that they had a altivec like unit (or someone reported it). All this definitely sounds like IBM is on board for Apple's next chip. I always wondered why IBM would stay on board just make some G3's for the iBook. It's only a matter of time before the iBook goes G4, then what for IBM? It won't matter if IBM will be making more or all of Apple's chips.
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post #93 of 240
Getting back to Apple 3.1415 (pi) (pie) whatever...

Remember back pre-MWSF and we had those criptic messages from Codename?

Well here was one of his messages:

"A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin..."

No connection I'm sure but since some of the stuff that Codename posted is starting to come true 'Rosetta' for one it got me to thinking... and now a new reference to 'pie' when that was one item I never could find a connection to...

Oh well... as you were..

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post #94 of 240
[quote]<strong>
All I said was that if the controller had a few simple DSP instructions on board to do transformations on the data coming from memory, it might be possible to sniff out those instructions and divert them, if the DSPs understood a subset of AltiVec instruction set. Why a subset? Because they're not going to have the full capability of AltiVec, but if they recognize the same instructions, no custom instructions have to be generated, either by the programmer or by the compiler, and the additional hardware will be transparent.
</strong><hr></blockquote>

Heh, you know not what you ask. The instruction stream is handled by the processor -- it reads instructions from memory according to its program counter(s) and decode those instructions, dispatching them to the appropriate execution unit. On the 7455 most execute in 7 cycles with a throughput of 1 per cycle per execution unit (up to 4 maximum). When the instruction is done a retirement unit orders them to ensure that they write back their results in the correct order. Several of the instructions use values to/from the integer and condition code registers. Memory loads have to go through the caching system. Several instructions exist just to control the caching system. All of this is used by every AltiVec using program, so a subset would not be much of a subset. Trying to move any of it off-chip onto a substantially slower piece of silicon would be prohibitively expensive. A software AltiVec emulator would probably be faster (and no, it would not be at all fast). Either way it would completely kill the entire point of having the AltiVec instructions.

<strong> [quote]
Actually, what it reminds me of is IBM's Channel architecture, where the busses themselves could be programmed to perform instructions on the data sent across them. If it's desperate, then IBM is guilty of tremendous amounts of desperation in designing their high end architectures. It's understandable: Bandwidth is crucial. On a personal computer platform, it's at a premium.
</strong><hr></blockquote>

I'm not familiar with their architecture, but I suspect it is quite different than a "little DSP in the memory controller". There are very cool things that can be done by auxilary processors, and it would be cool if Apple was actually doing something like this... but I doubt it.

The bus you're refering to is MicroChannel? I think all that did was apply logical operations to the data crossing the bus... super-specialized and not really worth the effort. Now, if the memory controller and CPU would do some kind of data compression before putting the data on the bus, that would effectively increase memory bandwidth and would definitely be "worth it". That's not likely to happen on MPX.

<strong> [quote]
Are you sure they didn't at least have a hand in its design? I've read that they had an important, and possibly central, role in developing the instruction set, and in pushing for an onboard vector unit in the first place. The implementation in silicon is obviously all Moto, however.
</strong><hr></blockquote>

johnsonwax said "(Apple really designed it, IIRC)". This is not correct -- it was a collaborative design effort to create the instruction set, with Motorola doing the hardware implementation.

<strong> [quote]
That would work for me. As nifty as a dedicated DSP on the memory controller might be in theory, it has a good chance of getting orphaned, like the DSP in the old AV series. Or IBM's ill-starred MicroChannel architecture.
</strong><hr></blockquote>

Exactly... and it means Apple (and maybe one or two 3rd parties) will spend programming resources code a few things up for it, whereas they could instead be doing cool things that will work on all AltiVec-equipped PowerPCs going forward.

Ah well, hopefully they at least go to the 166 MHz MPX, DDR333.
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post #95 of 240
This is all very exciting. I got much information about Motorola G5 processors so far, but until now no one I know could confirm that one of these chips will be used by Apple. On the other hand I haven't (yet) found somebody who was able to confirm that Apple really dropped the G5 project.

The idea that IBM will design a desktop processor for Apple is very interesting. IBM has recently announced that the Power4 successors (Power5 and Power6) will be designed be be much cheaper and cooler, and they will also use new instructions for complex tasks like managing stacks - a technology called "Fast Path". Maybe "Apple Pi" and "Fast Path" are the same thing.

Unfortunately we will have to wait until 2004 for the Power4 - I wonder if IBM will be able to ship a powerful desktop CPU before that date.

[ 06-11-2002: Message edited by: haderach ]</p>
post #96 of 240
[quote]
All I said was that if the controller had a few simple DSP instructions on board to do transformations on the data coming from memory, it might be possible to sniff out those instructions and divert them, if the DSPs understood a subset of AltiVec instruction set. Why a subset? Because they're not going to have the full capability of AltiVec, but if they recognize the same instructions, no custom instructions have to be generated, either by the programmer or by the compiler, and the additional hardware will be transparent.

<strong>Heh, you know not what you ask.</strong><hr></blockquote>

No, I do, sort of. I knew it would require an instruction decoder in the memory controller. I was trying to think of ways to make the little DSPs transparent.

At this point, I've come to the conclusion that there are too many reasons why it couldn't happen. But it was a fun thought experiment.


[quote]<strong>I'm not familiar with their architecture, but I suspect it is quite different than a "little DSP in the memory controller". There are very cool things that can be done by auxilary processors, and it would be cool if Apple was actually doing something like this... but I doubt it.

The bus you're refering to is MicroChannel?</strong><hr></blockquote>

No, it was called the Channel architecture, and as far as I can recall it predates the personal computer revolution. MicroChannel was a scaled-down version for the PC which was utterly doomed when that became a commodity market. I don't know the exact details, but several of the people I work with programmed Channel architectures back in the day, and it was capable of some powerful stuff. Not just Boolean logic. A (very simple) DSP would be in line with what it could do.

[quote]<strong>Now, if the memory controller and CPU would do some kind of data compression before putting the data on the bus, that would effectively increase memory bandwidth and would definitely be "worth it". That's not likely to happen on MPX.</strong><hr></blockquote>

No, but it would be nice. The biggest disadvantage I can think of is increased latency. That, and performance would vary significantly based on how well the data compressed at any given moment, which might yield some odd results.

[quote]
That would work for me. As nifty as a dedicated DSP on the memory controller might be in theory, it has a good chance of getting orphaned, like the DSP in the old AV series. Or IBM's ill-starred MicroChannel architecture.

<strong>Exactly... and it means Apple (and maybe one or two 3rd parties) will spend programming resources code a few things up for it, whereas they could instead be doing cool things that will work on all AltiVec-equipped PowerPCs going forward.</strong><hr></blockquote>

Apple could get around that by putting them in every single memory controller they shipped, across all models. Then it would be something like Quartz Extreme, that kicked in if you had the proper hardware, and was translated and handled by the CPU if it wasn't there. That way Apple would work around the problem that killed the AV DSP (shipping in exactly two expensive models for a couple of years), and the one that killed MicroChannel (relevance, incompatibility in a commodity market).

This is not the first time something like this has come up. The "Raycer chip," "QuickTime-on-a-chip," and various rumors about dedicated MPEG acceleration have all pointed this way for a couple of years now. That could mean that where there's smoke, there's fire; or it could mean that where there appears to be smoke, there's a lot of hot air. I have my reservations about auxiliary processors, though. They've done well in the embedded market, and in big iron, but they have a poor track record in personal computers.

[quote]<strong>Ah well, hopefully they at least go to the 166 MHz MPX, DDR333.</strong><hr></blockquote>

I wouldn't complain.

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post #97 of 240
[quote] Remember back pre-MWSF and we had those criptic messages from Codename?

Well here was one of his messages:

"A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin..."

No connection I'm sure but since some of the stuff that Codename posted is starting to come true 'Rosetta' for one it got me to thinking... and now a new reference to 'pie' when that was one item I never could find a connection to...

<hr></blockquote>

Hmm ... forgot all about the Codename messages ... not sure if this is any help, but Dolphin-IC (www.dolphin-ic.com) seems to have some licensing agreements with IBM for fab technology, and they're involved with Hypertransport.

Also, IBM are the chip suppliers and one of the designers of the Nintendo Gamecube architecture, which was named 'Dolphin' in it's prototype stages.

Now I'd like to know what 'Trinity' stands for.
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post #98 of 240
[quote]Originally posted by audiopollution:
<strong>Now I'd like to know what 'Trinity' stands for.</strong><hr></blockquote>

Trinity is the code name for the Cube.
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post #99 of 240
[quote] Trinity is the code name for the Cube.

<hr></blockquote>

Okay, so I wonder if this was not just a veiled reference to the 'sunflower' iMac, then.

Ate some pie. (round)
More voluminous than a Dolphin. (bigger than gamecube)

Nah. I'll just shut up now.
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post #100 of 240
[quote] "A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin<hr></blockquote>

My read:

"A little bird [unknown] told that Trinity [the G3 processor, IBM's specialty] shall return, after eating pie [Apple Pi, the new interconnect strategy], more voluminous [greater internal bandwidth] than a dolphin [than the PPC chip in Gamecube, which is known for its massive internal bandwidth].
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post #101 of 240
Hmmm, trinity was the code name for the cube.
Someone in this thread (or another one, i'm too lazy to look) said they were told the next powermac would look like two cubes stacked on top of one another. Sounds more voluminous than a dolphin to me.
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post #102 of 240
I was curious, at the time, as to why Apple wanted retailers to put the cube displays in storage rather than destroy them.
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post #103 of 240
[quote]Originally posted by moki:
<strong>

No, it would need to be custom-coded -- and in reality, only a very few applications would likely end up using them. We're talking about very light-weight DSPs here. However, for certain very specific applications, they'll enabled some very cool stuff to happen.

[ 06-11-2002: Message edited by: moki ]</strong><hr></blockquote>

Hmmm... Is it just me, or is anyone else thinking about better memory management for more processors? I'm just guessing, but could this be a sign that the long rumored and often drooled over quad processor boxes may indeed become a reality before too much longer?

Nahh, I didn't think so either.
post #104 of 240
[quote]
No, it was called the Channel architecture, and as far as I can recall it predates the personal computer revolution. MicroChannel was a scaled-down version for the PC which was utterly doomed when that became a commodity market. I don't know the exact details, but several of the people I work with programmed Channel architectures back in the day, and it was capable of some powerful stuff. Not just Boolean logic. A (very simple) DSP would be in line with what it could do.
<hr></blockquote>

Ah... this was from the day when memory was faster than the processor. That day is long gone now. I personally think processing architectures like we're seeing develop in the new graphics chips will be the trend for massive computations going forward. I know there are a lot of skeptics, but I suspect they haven't seen what I've been privvy to.
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post #105 of 240
"A little bird told that Trinity shall return, after eating pie, more voluminous than a dolphin..."

Are we sure Trinity is the codename for the Cube? That's interesting. One poster said his information suggested the new G4 case would look something like two Cubes stacked one on top of the other. Ergo:

Cube shall return, after eating pie. . . After eating pie. . . A new Cube-like tower that grew after eating Apple Pi?

"after eating pie, more voluminous than a dolphin..."

More voluminous than a dolphin. Dolphin is the codename for the G3 processor inside of the GameCube, which features SIMD instructions. After eating pie, of great volume, greater than that of Dolphin. The G5 is the high end, very large cousin of Dolphin! It will be featured in a renewed Trinity! Ergo, the G5 is a huge, high end cousin of the Dolphin, which will make its debut in a tower derivation of the Cube. Now I feel fulfilled.

moki originally posted:<strong> [quote] I'll say it again for this coming MacWorld/NY -- I think some very cool stuff is in the works, but you aren't going to see it in a month. <hr></blockquote></strong>

I just hope Apple understands the implications of waiting to bring these cool things to the market. Perhaps the company doesn't think it has immediate competition since it's the only game in the Mac town. The PC market doesn't stand still.

moki originally posted:<strong> [quote] This DDR machine should have been out about a year ago, but they kept on cramming too many new things on the mobo all at once, resulting in all sorts of problems that needed to be addressed and tested. <hr></blockquote></strong>

Now that is very distressing. Such an episode points to poor middle management, letting a project continuously slip due to added features in such a manner. Doesn't Apple realize that low end, $750 machines have DDR already? moki, can we at least hope for a fully implementation of DDR, or is this the same crippled Xserve version?

[ 06-11-2002: Message edited by: Big Mac ]</p>
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post #106 of 240
[quote]Originally posted by Big Mac:
[QB]
Now that is very distressing. Such an episode points to poor middle management, letting a project continuously slip due to added features in such a manner. Doesn't Apple realize that low end, $750 machines have DDR already? moki, can we at least hope for a fully implementation of DDR, or is this the same crippled Xserve version?
[QB]<hr></blockquote>

Not to nitpick, but the Xserve does have a full DDR implementation... the problem is that the G4 doesn't. They could easily push this into the consumer level machines, I expect. They won't unless they can still differentiate the PowerMacs.
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post #107 of 240
[quote]Originally posted by Programmer:
<strong>

Not to nitpick, but the Xserve does have a full DDR implementation... the problem is that the G4 doesn't. They could easily push this into the consumer level machines, I expect. They won't unless they can still differentiate the PowerMacs.</strong><hr></blockquote>

I understand the sentiment expressed here, but I don't consider the Xserve to have a full DDR implementation. In order for it to be a full implementation in my book, the processor has to be able to benefit. Since we're still stuck with that same FSB, the processor's no better off. Therefore, it's not a full DDR implementation.
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post #108 of 240
First post from new account...

And from new cable modem @ home...! (trust me, this is after a nine month drought whilst going through divorce procedings...)

I for one would LOVE to see a new Cubesque micro-tower for the new PowerMac form factor...

Dual or Quad 1.2GHz G5 CPUs (512KB L2 cache/4MB L3 cache per CPU), 400MHz FSB, 2GB PC2600 DDR SDRAM (4 @ 512MB DIMMs), and three (3) expansion slots (one AGP 8x 110Pro, two 128bit/66MHz PCI X slots)...

Three (3) UltraATA133 interfaces, one for SuperDrive2 (faster) + another device (two full-size drive bays on case), two for RAID array (four hot-swap drives on case), FireWire2, USB2, Gigabit Ethernet, digital audio optical I/O...

Hook up a pair of Cinema Displays, and away we go...!

[ 06-11-2002: Message edited by: MacRonin ]</p>
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post #109 of 240
All this talk about Dolphin and Pi is making me hungry.
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post #110 of 240
I have a friend that works <a href="http://www.wentworthlabs.com/" target="_blank">here</a>, and about a year ago he told me that there was "a company" that came to Wentworth wanting them to design the testing equipment for a 5GHz CPU, and that they had to turn them down because they(and the majority of the other companies in that industry) didn't have the capability to test chips at that high of a frequency.

Now, this guy knows that I'm *really* into Macs/Apple, and the way he said this(you know, with meaning), made me think it had something do Apple in some way.

Now, I told myself that this would be practically impossible, considering at this time Apple's top clock speed was &lt;1GHz, but I thought I'd keep an eye out for a chip company that was prepping the release of such a chip in the next year or so.

No company is as secretive as Apple(and their partners), and I certainly haven't heard anything about such a chip from AMD/Intel... So, has anybody else heard something about such a chip?

[edit]: just cause I knew you'd ask, I did ask him to give me more information, but he cited NDA restrictions]

BTW, he also talked alot about the shortcomings of Intels long-term viability against AMD in terms of chip design/speed, and with the prototype opteron/hammer benchmarks, it looks like he might have been right about that...

[ 06-11-2002: Message edited by: Steve's Job ]</p>
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post #111 of 240
Hey! Wake up! Interesting find here....

<a href="ftp://ftp.apple.com/Apple_Support_Area/Misc/Inserts/073-0703-a.pdf" target="_blank">ftp://ftp.apple.com/Apple_Support_Area/Misc/Inserts/073-0703-a.pdf</a>

I found an interesting link buried in some directories on apple's ftp server. This is instructions for applying a heat sink to the emac. This is odd doncha think? I will watch for some more stuff like this.

Want to know what I think? I think this is preemptively posting directions for dealing with a new processor line. Just a though but I found this odd little pdf which just popped up out of the blue to be kinda interesting. Thought I'd share it with you.
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post #112 of 240
[quote]Originally posted by Big Mac:
<strong>

I understand the sentiment expressed here, but I don't consider the Xserve to have a full DDR implementation. In order for it to be a full implementation in my book, the processor has to be able to benefit. Since we're still stuck with that same FSB, the processor's no better off. Therefore, it's not a full DDR implementation.</strong><hr></blockquote>

So the processor receives nobenefit from having more bandwidth on the other side of the memory controller to share with DMA devices?
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post #113 of 240
[quote]Originally posted by Jonathan Brisby:
<strong>Hey! Wake up! Interesting find here.... I found an interesting link buried in some directories on apple's ftp server. This is instructions for applying a heat sink to the emac. This is odd doncha think? I will watch for some more stuff like this.

Want to know what I think? I think this is preemptively posting directions for dealing with a new processor line. Just a though but I found this odd little pdf which just popped up out of the blue to be kinda interesting. Thought I'd share it with you.</strong><hr></blockquote>

There's nothing odd about this whatsoever, it's simply instructions for re-placing the eMac's heatsink, which, as the first page of the document states "whenever the heatsink is removed, the bottom side of the heatsink and the top of the microprocessor must be cleaned and thermal past must be applied."

It's simply a support document for anyone who might be taking appart an eMac for servicing, the heatsink would routinely be removed by a service tech checking out a malfunctioning eMac, and this is nothing more than a friendly reminder to replace the thermal paste. You'll find that there's also an article like this for the current iMac, which has a two-part heatsink that comes appart when dissassembled for service.

Here's a tip, if you see hoof prints, don't start looking for zebras. The simplest explanation is usually the correct explanation.

ciao,

michael

[ 06-11-2002: Message edited by: scadboy ]</p>
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post #114 of 240
[quote]Originally posted by scadboy:
<strong>
Here's a tip, if you see hoof prints, don't start looking for zebras. The simplest explanation is usually the correct explanation.
</strong><hr></blockquote>

That reminds me of the diffferent colored zebras they had for fruit stripe bubble gum. Does anyone know if they still make that?
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post #115 of 240
Yes, they do, in fact, it's apparently the #1 "Kids Gum." Whatever the hell that means.

<a href="http://www.fruitstripe.com/product/fruitstripe.asp" target="_blank">http://www.fruitstripe.com/product/fruitstripe.asp</a>



ciao,

michael
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post #116 of 240
[quote]Originally posted by scadboy:
<strong>Yes, they do, in fact, it's apparently the #1 "Kids Gum." Whatever the hell that means.

<a href="http://www.fruitstripe.com/product/fruitstripe.asp" target="_blank">http://www.fruitstripe.com/product/fruitstripe.asp</a>



ciao,

michael</strong><hr></blockquote>

See, sometimes when you find hoofprints you do find a Zebra (and a multicolored one at that)!
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post #117 of 240
Regarding Pi. If I recall correctly "Pi" meant Pipeline Instructions. Apple PI was some sort of custom pipeline instructions that Apple wanted in the G5 chip. Again, I don't really understand this stuff 'cuz I'm not in the chip business, but that's what I remember.
post #118 of 240
[quote]Originally posted by Big Mac:
<strong>Now that is very distressing. Such an episode points to poor middle management, letting a project continuously slip due to added features in such a manner. Doesn't Apple realize that low end, $750 machines have DDR already?
</strong><hr></blockquote>

Uh huh. And who exactly is making money off of said $750 machines? Nobody really. The market is in a funk. So Apple ships a 2 GHz G5 with a 533MHz FSB. In this market, who's buying? Sure, you'll be happy, but Apple really won't be any better off.

Apple needs something more than MHz here and there. Even when the MHz gap was much smaller and Apple was kicking ass in Photoshop bake-offs, things really weren't any better. We really need something more distinctive than an arbitrary claim that the box is faster.
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post #119 of 240
[quote]Originally posted by johnsonwax:
<strong>

Uh huh. And who exactly is making money off of said $750 machines? Nobody really. The market is in a funk. So Apple ships a 2 GHz G5 with a 533MHz FSB. In this market, who's buying? Sure, you'll be happy, but Apple really won't be any better off.</strong><hr></blockquote>

<img src="graemlins/bugeye.gif" border="0" alt="[Skeptical]" /> First off, perhaps I wasn't clear enough - I should elaborate on my statement. The point I was making about $750 DDR PCs is not that Apple should go that route. The fact is, though, the G4s need true DDR; DDR isn't so much more expensive that the margins on the G4 would be killed if DDR were introduced.

It didn't make the price of the Xserve skyrocket to implement DDR, even though the FSB kills the speed gain. Especially given the fact moki stated the DDR board could have been released long ago, please don't try to assert that Apple can't do it. Mismanagement has apparently screwed things up in this case.

"So Apple ships a 2 GHz G5 with a 533MHz FSB. In this market, who's buying? Sure, you'll be happy, but Apple really won't be any better off." Of course I would be happy. Most every other participant here would be as well. And the professional industries would be quite happy.

Great performance isn't a luxury in the computer space, especially with Intel making the gains it has made in the last couple of years. If the SPEC numbers I've seen posted here are to be believed, then the P4 is catching up to the Power4, which is currently the fastest processor money can buy. If that's the case, then we all must worry, since our G4 will be blown out of the water if the new P4s are posting those kinds of numbers. (It's disheartening to notice that no one bothers to even post SPEC numbers for the G4 anymore.)

[quote]Originally posted by johnsonwax:
<strong>

Apple needs something more than MHz here and there. Even when the MHz gap was much smaller and Apple was kicking ass in Photoshop bake-offs, things really weren't any better. We really need something more distinctive than an arbitrary claim that the box is faster.</strong><hr></blockquote>

True, the MHz gap was much smaller, and true, things weren't all that much better. But that doesn't mean compounding the problem by falling further and further behind in processor technology is going to help us at all. A person who has health but no job isn't all that well off. Yet, if that person - who still has no job - then gets the flu, is that person doing any better? Obviously not. Under-performing processors, along with such a huge MHz gap, is poised to give Apple the flu. It's not a terminal case, yet, but individuals have died from the flu before. (Note: I'm not trying to state Apple will die - I am simply pointing out the serious nature of the current situation.)

[ 06-12-2002: Message edited by: Big Mac ]</p>
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post #120 of 240
[quote]Originally posted by Big Mac:
<strong>
True, the MHz gap was much smaller, and true, things weren't all that much better. But that doesn't mean compounding the problem by falling further and further behind in processor technology is going to help us at all.</strong><hr></blockquote>

But in a declining market, any marketable gains that Apple shows now are lost. Apple touts DDR RAM at MWNY, but if nobody is buying, the marketing punch is lost and DDR alone isn't enough to yank the market up for Apple.

What Apple needs to do is to *not* show incremental improvements now (they work better in a growing market when people will buy simply because they have budget), but rather to save them up and launch them all together when they can demonstrate an overall superior product.

Consider the creeping CPU speeds at Intel and AMD. How many people can articulate the benefits of 2.2 GHz over 1.6GHz? or 533MHz FSB vs. 333MHz? Oh, it's faster, sure, but faster enough to argue for funds to buy? How much faster? How much will we save with faster hardware? Those are the kinds of questions that come out when the money isn't there.

Apple appears to be positioning itself for specific markets. Bioinformatics folks can turn BLAST running 4x faster into a budget line-item. The film industry looks like they'll soon get a demonstration of the same from Apple. By showing dramatic and specific benefits of new hardware/software, Apple makes a better case - even if they're no better off than had they done incremental improvements. The reason is that the marketing isn't there in the latter case.

A is 33% faster than B which is 33% faster than C which is 33% faster than D which is 33% faster than E. It doesn't sell as well in this market as if you said A is 400% faster than E. That requires that B-D never exist.

Keep in mind that Apple cannot grow market share by appeasing us. It does need to do that, but their user base is loyal and willing to be abused. They grow by converting, and people don't convert for marginal reasons.

Apple's best bet - get Mac OS X as solid as any unix out there, and as servicable as any MS OS out there, and at the same time drop the hammer on killer hardware. Introduce the new Apple, with a full product line, native 3rd party apps, MCCA support, clear performance and reliability benefits. At that point, up-front cost won't matter that much, but the message needs to be very clear on each of those points.

From my view, Apple shouldn't sweat the incremental improvements. They should focus on demonstrating a substantial benefit to those outside of the current user base.
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