[quote]Originally posted by Nebagakid:
<strong>Could someone give me a summary of what Dorsal, or whatever has been discussed in this thread?
<img src="graemlins/smokin.gif" border="0" alt="[Chilling]" /> </strong><hr></blockquote>
OK, Here ya go, Dorsal M's posts on this thread.
[quote]Originally posted by Dorsal M:
<strong>posted 06-14-2002 05:06 PM
Sorry for the long haitus, but it has been quite busy here. We are in final testing phases of our Apple hardware and there has been an excitement in the air. I believe many of you will be pleasantly surprised with the hardware to be released, and after seeing some other sites, I'd like to remind you all that behind most rumors is a kernel of truth, despite the fact that some sites like to embelish on the tidbit they get. Without further ado...
The PowerMac G4 as we know it will be retired. Well the architecture will at least. We will see changes to the system bus, processor and general layout. Motorola has been hard at work with the 130nm G4. It will scale nicely (at least 1.5GHz by the summer) and have improved bus features. Memory access will be stellar. And you'll see why. not only will DDR SDRAM make a debut but it will not connect to the processor iin a conventional manner. More to come. Cache will also be increased on the processor level. Twice what is seen now. You will see a collaboration with another hardware company, but this will not surprise some of you in the know.
posted 06-17-2002 10:58 AM
There will be an e500 core based desktop processor based on Apple's requirements. The e500 core is a 7 stage pipeline design very similar to the 7455 core (they both get about 2300MIPS). The execution units are very similar, in quantity and performance. There is an Altivec add on built for the e500. Apple's implimentation has dual RIO ports and a memory controller. The interconnect is the e500 native OCEAN and this is a wide/fast bus, only for on die interconnects. Multiprocessing in handled via RapidIO's 16 bit variant. It connects to a RapidIO hub (RIOH) that serves as the central hub for various RIO devices, such as peripheral controllers, PCI controllers, other PowerPC processors, network processors, etc. The hub controls the bit width and frequency, and this is determined by the distance from the hub (trace length). If both processors are proximate to the RIOH then you can have them connect at a low overhead 16bit wide RIO tunnel at a 2GHz freqency. To connect to a PCI controller you can keep the 16 bit wide port or if pin out is an issue you may need to drop it to 8 bit and run it at a lower frequency such as 500MHz. RIO is capable of over 7GBps bandwidth running at 16bit.
The beauty of Book E is the modularity. The way Motorola designed it was so a customer can pick and choose the components. this was as long as the customer had the money to spend as I imagine this is not an inexpensive proposistion. But it is an ideal solution for Apple. They can choose the size of the L2 cache, number of e500 cores, kind of memory controllers available, if they wanted a PCI controller also embedded... And rumor is that e500 core will soon be joined by another high performance core. </strong><hr></blockquote>
Sure wish Dorsal would give us more info.