Originally Posted by SpamSandwich
It's my understanding intel is already making chips in the 14 nanometer range. These TSMC chips are 20 nanometer?
Intel is making a few smaller lower performance 14nm chips, just recently begun. But the majority of their 14nm production is well behind original estimates, by about two years! They've continually been delaying production. Quite frankly, 14nm is such a bear, that I was surprised that Intel announced, several years ago, that they would be continuing their two year tick tock cycle. It's at four years now, and running, as we won't know its second half of 2015 schedule which is now what they're are claiming, will be met until it's actually out.
But, 22nm was delayed by six months as well, so we are really behind schedule. With TSMC now at 20nm, that's better than the majority of Intel's product lines. If TSMC comes out with 16nm for Apple's next september's production in 2015, they will be less than half a node behind.
Intel is still claiming that 10nm will be on schedule, but I highly doubt that. Considering what we've seen in recent years, and with most microprocessor experts believing that 10nm is close to the end, I think that 10nm, which is still in the R&D stage, even though if Intel had been on schedule, it should be where they are now, I see many delays ahead for this too, Intel is now an entire node behind where they said they would be four years ago.
What surprised me is that Intel is claiming on their production model roadmap that not only will they have 10nm, but 7 and even 5! I find this hard to believe, as they are presenting it as fact, even though most experts have significant doubts about 7, and many are skeptical about 5nm being achievable. We have to understand that the average atom is about .5nm in diameter, particularly the ones needed here, such as copper, silicon, etc. this means that a line that is 14nm wide is just 28 atoms wide, 10nm is 20, 7 is 14, and 5 is just 10 atoms wide.
The problems that present themselves are lithography, which becomes exceeding more difficult. Some of the techniques used now are very clever, but won't carry down much below 14nm. Then we have the problem of the accuracy of the etching. If you look at a high magnification if a chip, you will see that structures are anything but smooth and even. They are bumpy and lumpy. This doesn't matter with larger structures, because those bumps and lumps are a small percentage of the thickness or width. But as line size becomes smaller, those discrepancies become a larger percentage of the feature, resulting in less predictable performance. This is a big problem.
Then we have the quantum effects of tunneling, which is a major cause of leakage, though there are others as well. When a line is thick and wide, the electrons near the edges can tunnel out through the insulator, but the percentage is very small. But as line width and thickness becomes smaller, tunneling becomes a major issue. At some point soon, it will become unmanageable, as no materials or process techniques will be adequate to cut down on it enough. That's where the end comes.
Will it be 10nm or 5nm? No one knows for sure. But once we're there, everyone will end up at the same node, giving no one a major advantage over another.