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HyperTransport vs. RapidIO

post #1 of 5
Thread Starter 
Here's one thing I don't really understand:

- Motorola says G5 processors will use RapidIO bus
- IBM says their future PPCs will use RapidIO bus
- AMD has developed HyperTransport
- Apple has committed to HyperTransport

RapidIO and HyperTransport basically do the same thing (bus <= 32 bit at very high clockrates -> higher bandwidth) but they are NOT compatible, and they cannot emulate each other (as far as I know). Using both RapidIO and HyperTransport at the same time doesn't make much sense (and would increase costs).

Rumors say Apple will release the forthcoming G5 on Motherboards featuring HyperTransport. But how can this work??? Does that mean that the G5 that Apple will use will use HyperTransport instead of RapidIO??? The only way this could be done (as Motorola doesn't support it) is with the aid of AMD, they have the necessary CPU circuits.

Or, if Apple will use the standard G5 with RapidIO, what are they then doing with HyperTransport??? As far as I know only the Athlon supports HyperTransport so far.

Does anyone know more about this???
post #2 of 5
rapid io is the bus for the memory and cpu, and hypertransort is the front side bus to pci and the firewire and all that stuff
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post #3 of 5
[quote]Originally posted by myahmac:
<strong>rapid io is the bus for the memory and cpu, and hypertransort is the front side bus to pci and the firewire and all that stuff</strong><hr></blockquote>

Actually, the term front side bus usually refers to the CPU&lt;-&gt;chipset connection. This is indeed what RapidIO is for. HyperTransport on the other hand is a technology for chipset interconnections, as with NVidia's nForce chipset: North- and southbridge (NVidia calls them differently though) are connected via hypertransport, but the CPU is connected via the Athlon's classic EV6 bus.

Bye,
RazzFazz
post #4 of 5
[quote]Originally posted by RazzFazz:
<strong>

Actually, the term front side bus usually refers to the CPU&lt;-&gt;chipset connection. This is indeed what RapidIO is for. HyperTransport on the other hand is a technology for chipset interconnections, as with NVidia's nForce chipset: North- and southbridge (NVidia calls them differently though) are connected via hypertransport, but the CPU is connected via the Athlon's classic EV6 bus.

Bye,
RazzFazz</strong><hr></blockquote>

Hypertransport can also be used for cpu-chipset connections as well as inter cpu buses.
post #5 of 5
As long as the CPU supports it. To date i think none does including the modern Athlon. Can HyperTransport be implimented within a chip? For example, Apple integrates the memory controller, PCI controller and all the other typical southbridge chip functions on one chip called the Pangea (on iMacs and iBooks), would it be possible for them to use HT to connect those devices to the PCI bringe on the same die and have that monolith chip connect to the processor using the native RIO bus? That could be a possibility. We wont know until we see some dev notes and white papers. 3 weeks. man that's a long time.
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