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post #561 of 771
Quote:
Originally posted by Outsider
Maybe both?

Hope so.
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post #562 of 771
Quote:
Originally posted by Ensign Pulver
According to Loop Rumors:


"We know internally that Apple has been replacing the acronym WWDC with the phrase "We Will Delight Crowds."


Crowds of developers or crowds of consumers?

Developers. Free books, answer their questions, insight into Panther frameworks etc. They need to get the "developers! developers! developers!" excited about the future of programming for the OS X platform. Of course it wouldn't hurt if they passed out a few new 15" AlBooks. .
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post #563 of 771
"developers developers developers"

Yeah they have to do something big to match MS...

...So Phil Schiller is a given.

***Drum roll***
"I reject your reality and substitute it with my own" - President Bush
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post #564 of 771
I have all those steve ballmer videos from his microsoft presentations, that guy really freaked me out, i scared my dad with them too
post #565 of 771
Quote:
Originally posted by MacUsers
I have all those steve ballmer videos from his microsoft presentations, that guy really freaked me out, i scared my dad with them too

Ouch.....don't make me remember that monkey dance
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post #566 of 771
Quote:
Originally posted by Leonis
Ouch.....don't make me remember that monkey dance

C'mon, it was fun, but anti-perspirant would help a bit....

What contemptible scoundrel has stolen the cork to my lunch? _(W.C. Fields)
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post #567 of 771
Quote:
Originally posted by piwozniak
C'mon, it was fun, but anti-perspirant would help a bit....


post #568 of 771
post #569 of 771
Oh God.....where's my gun...
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post #570 of 771
Quote:
Originally posted by Marcus

Awesome!!!
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post #571 of 771
That's Great!
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post #572 of 771
Computer: Cedric
Specs: eMac, 700MHz PowerPC G4, 384MB of RAM, 40GB HD, CD-RW drive, nVidia GeForce 2 MX, Mac OS X 10.1.5/Mac OS 9.2.2
Media: 1800 tunes, 78 photos, 3 movies, no DVD's.
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Computer: Cedric
Specs: eMac, 700MHz PowerPC G4, 384MB of RAM, 40GB HD, CD-RW drive, nVidia GeForce 2 MX, Mac OS X 10.1.5/Mac OS 9.2.2
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post #573 of 771
Cnet confirms Hypertransport at WWDC, hints at 970.

"Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.

The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer.

It may also discuss plans to adopt IBM's PowerPC 970 processor, sources have suggested. The PowerPC 970 can handle 32-bit software--found on most desktops--and 64-bit software, which is found on high-end servers. Among the benefits of 64-bit computers is that they can take advantage of far more memory than 32-bit machines."
Attention Internet Users!

"it's" contraction of "it is"
"its" possessive form of the pronoun "it".

It's shameful how grammar on the Internet is losing its accuracy.
Reply
Attention Internet Users!

"it's" contraction of "it is"
"its" possessive form of the pronoun "it".

It's shameful how grammar on the Internet is losing its accuracy.
Reply
post #574 of 771
Aw, Geez.

CNET: Fifty lemurs banging on keyboards.
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post #575 of 771
Quote:
Originally posted by Ensign Pulver
Cnet confirms Hypertransport at WWDC, hints at 970.

"Apple Computer plans to discuss how it will incorporate HyperTransport, a rapid chip-to-chip communications technology, into future computers later this month at its developer conference.

The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer.

It may also discuss plans to adopt IBM's PowerPC 970 processor, sources have suggested. The PowerPC 970 can handle 32-bit software--found on most desktops--and 64-bit software, which is found on high-end servers. Among the benefits of 64-bit computers is that they can take advantage of far more memory than 32-bit machines."

Well, I think they got the details wrong. Do we know if the 970 has HT buses (even a variant?). HT on the motherboard makes sence in the context of connecting stuff to the memory controller, i.e. memory controller to an auxillary controller instead of using PCI. The processor to memory controller link could be HT, I am not saying it isn't, but it isn't being advertised as it either. And there is no information on specific links between processors directly, the Power 4(+) has three dedicated buses to connect to other processors in the package, there is nothing to suggest the 970 has one at all.
post #576 of 771
The only way I can make sense of it is if the 970's companion chip has a bus for direct connection to other 970 companion chips. That could be ApplePI (eWeek) or HyperTransport (CNET) or - heck - both, if ApplePI is a protocol.

I don't think that's out of the question at all. It's probably one of the more elegant and efficient ways to handle the sort of grunt work that can cripple multiprocessor efficiency (such as keeping the caches coherent, which in plain English means making sure that every CPU is operating on the most current data). It ensures that the memory controller doesn't become any more of a Grand Central Station than it will already be if it has a robust DMA engine on board.
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post #577 of 771
Quote:
Originally posted by - J B 7 2 -
Developers. Free books,.. They need to get the "developers! developers! developers!" excited ... Of course it wouldn't hurt if they passed out a few new 15" AlBooks. .

Developers edition 970 Powerbooks under every seat would have the whole house doing the 'monkey dance'.

My prediction is there will be 970 Powerbooks for any developer that wants one at developers pricing (not under every seat).
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post #578 of 771
god imagine the "lust / covet/ desire / frelling cool " factor if the only people with 970 pb this summer were developers...

if i saw a dev. with one at a startbucks i would mug him.

\
post #579 of 771
i can't believe no G5 pics have leaked out
post #580 of 771
Quote:
Originally posted by Amorph
The only way I can make sense of it is if the 970's companion chip has a bus for direct connection to other 970 companion chips. That could be ApplePI (eWeek) or HyperTransport (CNET) or - heck - both, if ApplePI is a protocol.

I don't think that's out of the question at all. It's probably one of the more elegant and efficient ways to handle the sort of grunt work that can cripple multiprocessor efficiency (such as keeping the caches coherent, which in plain English means making sure that every CPU is operating on the most current data). It ensures that the memory controller doesn't become any more of a Grand Central Station than it will already be if it has a robust DMA engine on board.

No way. Having the memory controller chip with both processor busses connected to it is the most efficient method (in this instance). It can then also provide a large shared L3 cache (even out of embedded DRAM would be fine). The logic for detecting coherency issues, i.e is data dirty or not, benefits from being in one place and not having to compare notes with another chip.

If I were Apple (I know, I know, I'm not), I would design a very small dedicated memory controller chip that acted like a router, it ensures the requested data gets to the correct CPU OR peripherial chip. By making the chip as small as possible you could leave room on board the chip for some kind of cache, even if only as buffering. I would design the chip the same for uni- or dual- processor operation and have a high speed HT link between it and the rest of the system. And I would buy the chip that supplied PCI, AGP, ethernet, FireWire, USB (2), blah blah blah off of someone else (nVidia?) and concentrate my resources on uniqueness.

But they specifically talk about between processors, and we just don't know enough about the chip to do anything better than guess
post #581 of 771
Quote:
Originally posted by Marcus

LOL! That's awesome. Maybe you should add a slider for "Sycophantic groveling to Bill Gates", too!
post #582 of 771
Quote:
Originally posted by JRG
Well, I think they got the details wrong. Do we know if the 970 has HT buses (even a variant?).

Have you noticed that the Apple PI-BUS is 6.4 Gb/s just like HyperTransport? That's no coincidence. That is because the Apple PI-BUS is an implementation of HyperTransport.

So you will most certainly see PPC970 ship on a HyperTransport motherboard.
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post #583 of 771
Quote:
Originally posted by rmendis
Have you noticed that the Apple PI-BUS is 6.4 Gb/s just like HyperTransport? That's no coincidence. That is because the Apple PI-BUS is an implementation of HyperTransport.

So what is different about it? Or is Apple PI just a marketing name? Why wouldn't IBM release that info. Surely it is a significant advantage for the processor? "Look we support HT, we've done lots of work to make it easy for you to hook these babies up!".

Its not that I don't believe you becuase I consider it likely to be true, but there is no solid data saying there is a connection between processors.

Quote:
So you will most certainly see PPC970 ship on a HyperTransport motherboard.

Which is not in doubt, and not the same thing as saying the connection between processors is HT. The motherboard to me will be an HT motherboard if HT is used to connect any system components together (like ethernet controller etc).
post #584 of 771


1995 IBM announces Internet plans

Two days after purchasing Lotus Development Corporation, IBM announced it would strengthen its efforts in the Internet arena. The company said it would release software products for Web design and administration, as well as enhanced security software. Microsoft would follow suit within the next several months, also increasing its efforts in Web technologies.
IBM's change in emphasis was an extension of chairman Lou Gerstner's turnaround strategy, announced in March 1994, which shifted the company's focus to networking and client-server computing. The company had since undergone a remarkable turnaround, from a struggling company with consistent losses, to a cash surplus of $10.5 billion.
post #585 of 771
Quote:
Originally posted by JRG
No way. Having the memory controller chip with both processor busses connected to it is the most efficient method (in this instance).

Except that's not how the PowerPC 970 works. The 970's unidirectional bus and SMP functions require a companion chip.

May it be noted that I have said before that Apple could put multiple companion chips and 970s on a daughtercard. One connection to a master companion chip, or maybe some kind of switch, and then connections to other chips.

Whether this would be integrated into a single slice of silicon, I don't know.

Barto
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post #586 of 771
Quote:
Originally posted by Barto
Except that's not how the PowerPC 970 works. The 970's unidirectional bus and SMP functions require a companion chip.

May it be noted that I have said before that Apple could put multiple companion chips and 970s on a daughtercard. One connection to a master companion chip, or maybe some kind of switch, and then connections to other chips.

Whether this would be integrated into a single slice of silicon, I don't know.

Barto

We're saying about the same thing but using different terminology. Substitute companion chip for memory controller and our statements essentially gel.

There is no stipulation for a companion chip to only have one 970 processor connected, only that a 970 processor have a companion chip. So two processors sharing a companion chip (or memory controller) is a definate design possability. So I think the design still stands.

Just out of interest can I ask why you thnk uni-directional matters?
post #587 of 771
Quote:
Originally posted by JRG
So what is different about it? Or is Apple PI just a marketing name? Why wouldn't IBM release that info. Surely it is a significant advantage for the processor?

There is...i can't be arsed looking around for it. Do a search on the web if you have the time...or just wait 10 days.

The Apple PI bus IS HyperTransport interconnect that can be and will be used to multiprocessing and I/O on the same interconnect. Apple will produce a typical HyperTransport switch as a companion chip to do the needful. It may even use the same bus for memory.

Unlike the Athlon-64 which has two HT interconnects or the Opteron which has 3 HT interconnectd as well as integrated Memory controller/bus, i think the PPC970 just has the one Apple PI interconnect for everything.

It appears that the PPC 980 will have more HT interconnect. Two most likely with maybe a direct bus for memory. Though not sure of these details, these are likely possiblities.
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post #588 of 771
Quote:
Originally posted by rmendis
There is...i can't be arsed looking around for it. Do a search on the web if you have the time...or just wait 10 days.

The Apple PI bus IS HyperTransport interconnect that can be and will be used to multiprocessing and I/O on the same interconnect. Apple will produce a typical HyperTransport switch as a companion chip to do the needful. It may even use the same bus for memory.

Unlike the Athlon-64 which has two HT interconnects or the Opteron which has 3 HT interconnectd as well as integrated Memory controller/bus, i think the PPC970 just has the one Apple PI interconnect for everything.

It appears that the PPC 980 will have more HT interconnect. Two most likely with maybe a direct bus for memory. Though not sure of these details, these are likely possiblities.

I'd love to see more info on this -- just basing it on the throughput being 6.4 GB/sec is not sufficient because that can be just coincidence. The new Intel and 970 FSBs are also 6.4 GB/sec, and that doesn't mean they are all HyperTransport either. If the 970's FSB is actually HyperTransport why didn't they just come out and say it, and I think there is something about it that they did say which means that it isn't HT (can't remember offhand what that was...).
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post #589 of 771
And remember that Hyper Transport can still be used on the motherboard even though it is not used to connect the processor top the companion chip. HT will probably be used as the connection between the companion chip and any number of peripheral chips and other companion chips that in turn are connected to other 970s.
post #590 of 771
10 days till WWDC and still nothing?? i am sorely dissapointed with the apple community...come on guys, where are the photos?? hell, don't have photos, make some up!!! what is wrong with the rumor community these days?!?! sigh...all this is making me nostalgic for the freakin iWalk days

g
it's all fun till somebody loses an eye
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post #591 of 771
there are not even mock-ups to the powermac designs from all the rumors and stories
post #592 of 771
Quote:
Originally posted by thegelding
10 days till WWDC and still nothing?? i am sorely dissapointed with the apple community...come on guys, where are the photos?? hell, don't have photos, make some up!!! what is wrong with the rumor community these days?!?! sigh...all this is making me nostalgic for the freakin iWalk days

g

These kid's today... Whatya gonna do? Back in my day we'd have already seen tons of fakes hoaxes and more 'a friend of a friend' yarns than you could shake a stick at...
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post #593 of 771
Quote:
Originally posted by thegelding
10 days till WWDC and still nothing?? i am sorely dissapointed with the apple community...come on guys, where are the photos?? hell, don't have photos, make some up!!! what is wrong with the rumor community these days?!?! sigh...all this is making me nostalgic for the freakin iWalk days

g

Oh, alright then PBg5

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post #594 of 771
Quote:
Originally posted by Rhumgod
Oh, alright then PBg5


St. Ives protect us from that monstrosity.
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post #595 of 771
Quote:
Originally posted by MacUsers
there are not even mock-ups to the powermac designs from all the rumors and stories

Well, there's no shortage of pixel wranglers here...

*cracks whip*
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post #596 of 771
Quote:
Originally posted by 709
St. Ives protect us from that monstrosity.

Pretty bad, huh? JI would commit ritual suicide rather than put something like that in the public's lap.
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post #597 of 771
Quote:
Originally posted by Outsider
And remember that Hyper Transport can still be used on the motherboard even though it is not used to connect the processor top the companion chip. HT will probably be used as the connection between the companion chip and any number of peripheral chips and other companion chips that in turn are connected to other 970s.

A thought (or two)

If HyperTransport is being used to connect processors together, and given that the PPC970 doesn't use a HT bus, we have a companion chip of some kind connected to each processor in a multi-processor configuration.

This arrangement fits in very neatly with a NUMA architecture (each companion chip having it's own memory controller), giving scaleable memory bandwidth with increasing number of processors, makes machines with more than two processors simpler to design. It also means that, if the next generation chip comes with an onboard memory controller, the general design of the system remains the same, just change the two-chip 970+companion unit to a single (PPC980?) processor chip.

However, a NUMA architecture (also combined with a shift to 64 bits) will require a completely rewritten memory manager, especially if you want to get decent performance by making sure of memory locality when allocating. It would almost certainly not be worth the effort of retrofitting such a new memory manager to 10.2 for use over a very short period. So dual processor machines only appear when 10.3 appears (this will also, happily, be when the processor production has ramped up further and more processors are available.

michael
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post #598 of 771
Quote:
Originally posted by Programmer
If the 970's FSB is actually HyperTransport why didn't they just come out and say it, and I think there is something about it that they did say which means that it isn't HT (can't remember offhand what that was...).

The 970 bus is elastic while HT is not.
post #599 of 771
Quote:
Originally posted by mmicist
If HyperTransport is being used to connect processors together, and given that the PPC970 doesn't use a HT bus, we have a companion chip of some kind connected to each processor in a multi-processor configuration.

I'm sure i found a better source than this before which says that the ApplePI-BIU is in fact a supercharged HyperTransport link.

The reason it seems it may not have been just called HyperTransport is because it predates HyperTransport (or Apple's involvement in the consortium) and secondly because HyperTransport is quite a broad specification encompassing a variety of technology (which Apple PI-BIU complies with).

http://www.architosh.com/news/2002-1...7457-rm2.phtml
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post #600 of 771
WWDC Keynote Broadcast


praise the goddesses....
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