Why I think that a PPC 970 Laptop is possible now.
This is my first post, so please be kind - what the heck, I have a thick hide anyway!
First, the caveats.
There are lots of things that I don't know, amongst them being that;
(1) The 970 or equivalent is available in the necessary numbers.
(2) The 970 supports fully (or close to it) the HyperTransport spec.
(3) Power dissapation of the 970 at full rated clock speed
is acceptable under ideal operating conditions
(4) Cost of the 970 is acceptable.
Now the reasoning.
I think the solution to this particular question lays not with the processor (vitally important but not the issue) but with the system used to connect all the parts together - HyperTransport. Here's why.
First, a look at the capability designed into the HyperTransport specification. HyperTransport is;
(5) Scalable in clock speed.
(6) Scalable in bus width.
(7) Scalable in voltage.
(8) Designed to connect just about everything on the motherboard.
(9) Blindingly fast.
(11) Just beautiful to an engineer. (OK, I added that to the spec!)
Now, to consider where each of these fill the picture out a little.
(5) CMOS as a technology is simply more power consuming the faster you clock it. Clock it more slowly and it uses less power. Stacks of published examples of this in literature. CMOS is good in another way too, in that you can run it to just about zero hertz and it is still predictable. A lower HyperTransport clock rate implies lower clock rates in the supporting silicon (or germanium if some rumours are to be believed regarding possible processor implementations are to be believed).
(6) Run a wide bus between big data generators and big data users, a narrow bus to less demanding peripherals (such as USB
). The former category would include the CPU(s), the GPU and RAM amongst others. HyperTransport by the way is essentially a point to point specification but a particular device can have any number of the implementated at a given time.
(7) Run communications over the HyperTransport link at lower voltages when possible, at higher voltages when necessary. There is no reason why distinct HyperTransport connected units cannot operate at differing voltages.
(8) Because HyperTransport scales so well, even minor components can take advantage of it. Examples might be an ambient light sensor/illumination controller unit, battery condition monitor/charge controller etc. These types of device would not be bandwidth huggers but are necessary. However, consider major components such as PCI and PCI-X. Quoting the HyperTransport Applications Overview White Paper, December 2002
;Since the Hypertransport protocol encompasses the PCI enumeration and configuration protocols, existing operating systems need no modifications to take advantage of the greater bandwidth and integration made possible by Hypertransport technology.
Just simply bridge HyperTransport to PCI (in silicon) and make all your regular calls. So, components of all scales of implementation are covered, or just about.
(9) Does the 12.8 Gigabytes/second aggregate bandwidth back the speed argument up?
(10) The HyperTransport consortium talk about a HyperTransport Fabric
. This is comprised of one or more daisy chains of HyperTransport technology devices with a bridge to a host controller system at one end. You can almost picture the main board as a substrate for this wonderful new fabric
(11) Yes, I'll say it again, HyperTransport looks beautiful to someone who admittedly, hasn't yet designed with it!
So, why is HyperTransport the key?
Well, I think that HyperTransport is the key to the ubiquitous (sorry to those who hate that word) power management. The PPC 970 implements many power saving strategies. (I read that on IBM's site.) such feature is only useful if you can implement it and HyperTransport provides that opportunity. Perhaps a look at some senarios might be illuminating.
Here I am, sitting at my desk which is a firm flat surface by a draughty doorway. My PowerBook G5 (yeah baby
) is running flat out driving my 20" LCD (which at least is something I actually do have). I know that the case is running hottish underneath but I don't care because the computer is well within spec. I am feeling a bit tired but can't let go of the new acquisition, so I take it up to bed. (Yes I am married - 22 years, four kids so don't worry, if she were going to divorce me I think I've already provided plenty of excuses!) I sit up in bed with the thing (sorry - masterpiece) on my lap. Now I know it runs warm but I still don't care because I know that the computer will handle it. Sure enough, up comes the expected message.
Dear IQatEdo, I am adjusting operating parameters to maintain proper operation as cooling efficiency has been reduced reduced. Please note that the following adjustments have been implemented.
? Processor clock speed has been reduced 10%.
? Display colour depth has been reduced to thousands, allowing one bank of video RAM to be turned off.
? Bus speed has been lowered 10%.
? One bank of main memory has been reallocated to standby mode.
? Display intensity has been reduced 10%.
? Keyboard illumination is unaltered as I know you get really cranky if you cannot see the keys.
Please note that these changes will also prolong battery operation by half an hour.
I think the upshot of all this is that as long as power consumption is acceptable under ideal conditions, a combination of smart programming, comprehensive processor power management and a system of interconnects - HyperTransport - that allows power managment to be implemented comprehensively will manage those less than ideal circumstances.
Finally, HyperTransport is meant to be a simplifying technology in the design process and seeing how clever Apple's engineers are, I feel that they have quickly taken advantage of it. There should be reduced board real estate resulting from its adoption also.
All the best!