Quote:
Originally posted by Barto
For an architectually different low-end and high-end Power Mac, you would need 2 distinct chipsets. This is what some people here are proposing. This is not a good idea, as it would probably be cheaper just to have a single-teir architecture.
This has NOTHING to do with dual/single processors.
Remember, the Power Mac G5 will use a different architecture from northbridge/southbridge. This is not a shared bus "every device is the same" as MPX.
This is a unidirectional point to point bus which requires a companion chip for each 970
So what? A uni-directional bus makes no difference. At all. In any way.
The companion chip is not some magical entity where the 970 will not work without it. The 970 is a CPU. It executes instructions. It executes instructions on data.
The 970 relies on another chip to: read an address from the processor, get the memory at that address and supply it to the processor. That is a memory controller. You do not need:
970 <=> Companion Chip <=> North bridge
Because a north bridge chip is essentially a memory controller, and is really a PC Centric term. You would have this:
RAM
||
970 <=> Memory Controller
^
||
System Controller
(if these don't come out right, everything hooks into the Memory Controller)
If you want dual 970's
RAM
||
970 <=> Memory Controller <=> 970
^
||
System Controller
Now in both instanes the memory controller chip can be the same, if there isn't a second 970 chip then that part of the memory controller is inactive. The <=> represents an Apple PI interface, so there are two seperate interfaces to the memory controller. Each 970 in the system thinks it is the only one there and happily goes about doing its thing: Executing Instructions. All you need are different daughter cards.
Now there is also another instance where you could easily use the same memory controller to create a higher end machine with better performance:
RAM RAM
|| ||
970 <=> Memory Controller <=> 970
^
||
System Controller
Now here is the same memory controller supporting dual banks of RAM. The chip detects how many banks of RAM are hooked up and only uses what it has access to. And this can also be supported just on the daughter card (becuase that is where I think the RAM will be located).
Quote:
It would make the most sense for Apple to include a northbridge with seperate companion chips which are connected to the northbridge with HyperTransport. Dual and quad CPUs, maybe even more, would be feisable with this design.
In terms of a HyperTransport graphics card, who cares about industry standards when you have 12.8GB/s??? 
Barto
Well, it is much harder to get people to build for you if you don't support IS interfaces. Replacing AGP with a much higher bandwidth solution would be nifty.
