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PowerBook G5  

post #1 of 376
Thread Starter 
The PowerBook G5 has 2 MCMs with 2 processor each

4 processor PowerBook G5 with modified 440 core with altivec
post #2 of 376
Quote:
Originally posted by Nr9
The PowerBook G5 has 2 MCMs with 2 processor each

4 processor PowerBook G5 with modified 440 core with altivec

I think that might Be a Little hot.
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Kappa Rho Alpha Theta Zeta Omega Nu Epsilon
post #3 of 376
Thread Starter 
it is fine. only 1MB L3 cache each.
post #4 of 376
Where is this coming from? After posting similar topic out into the public scrutiny that ensued I have learned that any sentance with the word G5 and laptop/notebook means unbearable heat and/or ridiculously large amount of cooling space (ie. tower).

But if somehow you have managed to make this managable please share with us, and with...APPLE!

Maciek.
- Maciej.
- Maciej.
post #5 of 376
Quote:
Originally posted by Nr9
The PowerBook G5 has 2 MCMs with 2 processor each

4 processor PowerBook G5 with modified 440 core with altivec

Ummmm.... a PPC 440 is not a G5
post #6 of 376
Thread Starter 
It is not a G5 chip. apple call it G5 for laptop

the L2 cache is only 2KB it is suitable for laptop.
post #7 of 376
If true, is it a 64-bit processor, and when will it ship?
You think Im an arrogant [expletive] who thinks hes above the law, and I think youre a slime bucket who gets most of his facts wrong. Steve Jobs
You think Im an arrogant [expletive] who thinks hes above the law, and I think youre a slime bucket who gets most of his facts wrong. Steve Jobs
post #8 of 376
Thread Starter 
it is a 32 bit processor it will ship next year
post #9 of 376
One: How do you know this?

Two: If it's 32-bit, what makes it equivalent to a G5, or better than, the G4 used in the current PowerBooks?
You think Im an arrogant [expletive] who thinks hes above the law, and I think youre a slime bucket who gets most of his facts wrong. Steve Jobs
You think Im an arrogant [expletive] who thinks hes above the law, and I think youre a slime bucket who gets most of his facts wrong. Steve Jobs
post #10 of 376
Riiight.

Why in God's name would Apple want to use 2/4 440s?

The 440 is a "highly integrated processor", it features not only a CPU core, but also a DDR SDRAM Controller, PCI-X-bridge, DMA-Controller, Ethernet controller, and much more.

The processor core also features a 7-stage pipeline which tops out at 600MHz.

The Powerbook 440 would be a
1) Waste of time
2) Waste of money
3) Huge failure!

http://www.ibm.com/chips/techlib/tec..._final-web.pdf

Lock this thread.
post #11 of 376
Please lock this. IBL
What the problem is?
What the problem is?
post #12 of 376
Thread Starter 
um, integrating everything makes the power consumption for the entire computer smaller.

The processor core tops out at 700Mhz
at 700Mhz each core offer 2.8GFlop @ 1.5 Watt
post #13 of 376
Thread Starter 
By the way, the picture of the PDF is not of the core, the core is the small thing on the left corner, the powerbook is different design

it has a 440 core, a 440 FPU core, and an altivec core as one processor

each are pack into 2 processor chip. then there is a system controller controlling the two chip on one MCM module
post #14 of 376
Nr9, while the 440 could potentially do well as a subnotebook (a very small one, that is)/minidevice, since it is a SOC-design (System on Chip), it would suck as a Powerbook chip. One reason:

- It is slow. -

You can very well be used in a computer, but it cannot be used in a high-performance product like the Powerbook is supposed to be.

If you want to make the 440 a high-performance product, you'd need to redesign a lot more than you want to. Why not process shrink the G5 instead, which is a proven, high-performance product today, which will be suitable for a Powerbook next year.
post #15 of 376
Thread Starter 
There are 4 cores so it not slow

G5 is not design for mobile computing

no matter how small you shrink it it wont work

11.2 gigaflop on DP floating point is not slow
post #16 of 376
I can change my sig again!
I can change my sig again!
post #17 of 376
Is this thread a joke?
You think Im an arrogant [expletive] who thinks hes above the law, and I think youre a slime bucket who gets most of his facts wrong. Steve Jobs
You think Im an arrogant [expletive] who thinks hes above the law, and I think youre a slime bucket who gets most of his facts wrong. Steve Jobs
post #18 of 376
Thread Starter 
no
post #19 of 376
Quote:
Originally posted by Nr9
no

well then tell us where the hell are you getting this info?
You think Im an arrogant [expletive] who thinks hes above the law, and I think youre a slime bucket who gets most of his facts wrong. Steve Jobs
You think Im an arrogant [expletive] who thinks hes above the law, and I think youre a slime bucket who gets most of his facts wrong. Steve Jobs
post #20 of 376
Thread Starter 
would that be so i would get caught?
post #21 of 376
Sounds like a good start on an IBook if in fact a vector unit was added.

At some point I think Apple could set a trend in ultra low cost hardware by going high integration. While I truely doubt that the PowerBook is taking that route, it would certainly work for other potential Apple products. The IBook is a possibility if they keep it focused on its current market. As nice as the 440 series is though, currently it could not hope to be any more than a prototype for what Apple needs.

Thanks
Dave



Quote:
Originally posted by Zapchud
Riiight.

Why in God's name would Apple want to use 2/4 440s?

The 440 is a "highly integrated processor", it features not only a CPU core, but also a DDR SDRAM Controller, PCI-X-bridge, DMA-Controller, Ethernet controller, and much more.

The processor core also features a 7-stage pipeline which tops out at 600MHz.

The Powerbook 440 would be a
1) Waste of time
2) Waste of money
3) Huge failure!

http://www.ibm.com/chips/techlib/tec..._final-web.pdf

Lock this thread.
post #22 of 376
OK, let's step back and look at this. If it helps, don't think of it as a PowerBook, just an engineering exercize.

By itself, the 440 series is nothing to write home about. 4 of them, however, with four AltiVec units and FPUs, offer some real potential. They're very low power. The purpose of the MCM design is to get really high throughput between the chips in the module, so bandwidth and latency within the MCMs should be very high and very low, respectively. This is critical for clustering / massive SMP.

Now, consider the independent source that offered that IBM and Apple were developing a portable CPU from the 300 series, not the 900 series. What's the 300 series? That's a good question, but if IBM's naming conventions hold, the chips in its family resemble the 400 series more than they resemble the 900 series.

Consider also that IBM is currently building a supercomputer out of PowerPC 440s that will utterly crush the current #1.

Consider Cell, the IBM project to build a platform on massively parallel solutions for the first time (massive parallelism is nothing new, but each implementation has been a custom job with custom code, not really a platform). The above-mentioned supercomputer will be made of 128 nodes, each with 1,024 CPUs.

Now, we're talking about 4 cores, 4 AltiVec units, previously unheard-of bandwidth and latency between CPUs (on MCMs) - all requiring maybe 8 watts? They can easily grow into a 64-bit variant, since the PowerPC spec is natively 64 bit.

This is a highly unconventional platform for a personal computer, but I feel compelled to point something out that I haven't in a while: The only remaining champion of the traditional personal computer architecture is Intel. Everyone else is taking advantage of technologies like HyperTransport that allow for workstation-like motherboard designs at PC prices. These architectures are built around lots of bandwidth, which deƫmphasizes the need for one single powerful CPU. OS X can already do MP. Apple is already working on software for clustering. You can run this setup as a small cluster with wonderful gobs of bandwidth and negligible latency, and it will run very well indeed.

This, to me, is a far more interesting rumor than the 970 was - the 970 was exciting, and more than welcome, but it's fundamentally conventional: Big, fast, hot. This sort of 440-based board is one of the mammals scurrying around under the feet of the mighty dinosaurs.

As to whether the PowerBook is ready for this, that's an interesting question. Multiple low-power processors are better at doing multiple tasks at once than they are at doing one big task (unless of course that big task is split up into lots of little ones behind the scenes) - c.f. the dual-processor iPod. So, if you can imagine something that will need to run some fairly compute-intensive services regularly while maintaining a responsive interface and doing light-to-medium work, that would do nicely. (OS X is already moving this way, using the GPU to run QE, and that's only the beginning of what they could do.) The main obstacle here is the programming paradigm implied by this architecture, which most current software (and most current languages) are ill-suited to. This might have the raw theoretical power to replace a single fast CPU, but it might be a while before software that can exploit it is widespread.
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The Mayflies - Black earth Americana. Now on iTMS!
Becca Sutlive - Iowa Fried Rock 'n Roll - now on iTMS!
"...within intervention's distance of the embassy." - CvB

Original music:
The Mayflies - Black earth Americana. Now on iTMS!
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post #23 of 376
Not at all, no one here wants you to get caught.

The problem is that while I personally believe that Apple could gain a credible advantage, over the other hardware alternatives through the use of SOC technology, I do not find some of your points credible.

First with the current process sizes it would be just as easy to go SOC with a 603 core. Slap a vector unit on it, a memory interface, and a few I/O and your all set. While pin count would scale a bit, the overall effect would be lower power and smaller hardware.

The problem with 440 series is that to scale it, into the proper performance position one would have to do a great deal of design work. In the end I would have to wonder if the 440 could be scaled and retain its performance vs watt advantage. I would have to say that there is probally a product sector that the 440 could be used in that Apple currently doesn't play in. So from my perspective a SOC based system makes sense to me, but if it ever comes from Apple I'd have to think that it will be derived from a mainstream processor.

So in a sense I think that you have already been caught. It is up to you to prove otherwise.

Quote:
Originally posted by Nr9
would that be so i would get caught?
post #24 of 376
IBM offers the 440 as a core for SOC designs. It is not necessarily a SOC itself (IBM also offer a family of SOC designs using that core - that might be what you're thinking of). Apple can, if they choose, use the core and build whatever they want around it.

The second thing is that they won't be using the exact, existing 440 core, because it doesn't have AltiVec, and you can't just bolt AltiVec on. It has to be part of the core itself. So whatever Apple is working on is a variant of the 440 already - while they're mucking around in the core, they could do any number of other things that suited them, like start work on a 64-bit variant when that becomes timely.
"...within intervention's distance of the embassy." - CvB

Original music:
The Mayflies - Black earth Americana. Now on iTMS!
Becca Sutlive - Iowa Fried Rock 'n Roll - now on iTMS!
"...within intervention's distance of the embassy." - CvB

Original music:
The Mayflies - Black earth Americana. Now on iTMS!
Becca Sutlive - Iowa Fried Rock 'n Roll - now on iTMS!
post #25 of 376
Amorph;

You have presented a well reasonsed response. From my perspective, as state in other threads SOC technology has a lot to offer Apple. I just have trouble with the idea that the current 440 would step into a main CPU role well.

So considering die size shrinks and the design effort already put into the 603 series, I would have to think that this would have more likly hood of working its way into a SOC system. The other alternative, as you mentioned, is the 300 series. The 300's could very well be a new and clean design that would lend itself very well to described usages.

While Apple has done a huge amount of work to make much of OS/X SMP aware, there is probally alot more they could do. So any system based on the 440 series would have a big performance delta. That is application performance would be all over the map. On the ohter hand it could be argued that Apple is further ahead on delivering SMP aware systems than any other mainstream vendor.

I like the thought that Apple would have the brass to do such a machine, but I don't think they would deliver such a machine on their flagship laptop. I'd geuss a IBook myself or even a iMac. Further it will be a SOC system and not a traditional MCM, for no other reason than the expense.

The original poster is certianly creative in his responses. As such some of the responders suggesting that the thread be closed should be a little more opened minded. We are likely to see such systems sooner or later, I know that Intel has worked on such designs or concepts. Well Intel has left out the SMP part, probally so they can keep their sick marketing practices.

Thanks
Dave


Quote:
Originally posted by Amorph
OK, let's step back and look at this. If it helps, don't think of it as a PowerBook, just an engineering exercize.

By itself, the 440 series is nothing to write home about. 4 of them, however, with four AltiVec units and FPUs, offer some real potential. They're very low power. The purpose of the MCM design is to get really high throughput between the chips in the module, so bandwidth and latency within the MCMs should be very high and very low, respectively. This is critical for clustering / massive SMP.

Now, consider the independent source that offered that IBM and Apple were developing a portable CPU from the 300 series, not the 900 series. What's the 300 series? Well, let's say that the chips in its family look a lot like the 440, and nothing like the 970.

Consider also that IBM is currently building a supercomputer that will utterly crush the current #1 out of PowerPC 440s.

Consider Cell, the IBM project to build a platform on massively parallel solutions for the first time (massive parallelism is nothing new, but each implementation has been a custom job with custom code, not really a platform). The above-mentioned supercomputer will be made of 128 nodes, each with 1,024 CPUs.

Now, we're talking about 4 cores, 4 AltiVec units, previously unheard-of bandwidth and latency between CPUs (on MCMs) - all requiring maybe 8 watts? They can easily grow into a 64-bit variant, since the PowerPC spec is natively 64 bit.

This is a highly unconventional platform for a personal computer, but I feel compelled to point something out that I haven't in a while: The only remaining champion of the traditional personal computer architecture is Intel. Everyone else is taking advantage of technologies like HyperTransport that allow for workstation-like motherboard designs at PC prices. These architectures are built around lots of bandwidth, which deƫmphasizes the need for one single powerful CPU. OS X can already do MP. Apple is already working on software for clustering. You can run this setup as a small cluster with wonderful gobs of bandwidth and negligible latency, and it will run very well indeed.

This, to me, is a far more interesting rumor than the 970 was - the 970 was exciting, and more than welcome, but it's fundamentally conventional: Big, fast, hot. This sort of 440-based board is one of the mammals scurrying around under the feet of the mighty dinosaurs.

As to whether the PowerBook is ready for this, that's an interesting question. Multiple low-power processors are better at doing multiple tasks at once than they are at doing one big task (unless of course that big task is split up into lots of little ones behind the scenes) - c.f. the dual-processor iPod. So, if you can imagine something that will need to run some fairly compute-intensive services regularly while maintaining a responsive interface and doing light-to-medium work, that would do nicely. (OS X is already moving this way, using the GPU to run QE, and that's only the beginning of what they could do.) The main obstacle here is the programming paradigm implied by this architecture, which most current software (and most current languages) are ill-suited to. This might have the raw theoretical power to replace a single fast CPU, but it might be a while before software that can exploit it is widespread.
post #26 of 376
Its been awhile since I've visited IBMs information sites, but I believe that the 603 was also offered as a core. But that really doesn't matter.

The issues I see are that the 440 core would have to be extended qute a bit along with the periphrial base. Since cache is limited on the 440 this would have to be addressed also. So by the time you enlarge the cache and added an on chip interface to Apple compatible "hardware" it would seem to me that starting form the 603 would be easier. The possible gotcha here is the potential that IBM may have used a greater amount of design automation with respect to the 440. {the thought of compiling a PPC chip design on a mainframe is pretty hot}.

Like I said I'm all for a SOC design, but do have to wonder if the MCM part has any reality at all. While I'm certain that two 440 plus some I/O could fit easily on one chip, I still have a problem convincing myself that this would be the avenue selected. People arguing against any possibility at all of this happening are a little out of touch with process technology, plus SMP on a chip G4 design efforts have been known for a long time.

Dave


Quote:
Originally posted by Amorph
IBM offers the 440 as a core for SOC designs. It is not necessarily a SOC itself (IBM also offer a family of SOC designs using that core - that might be what you're thinking of). Apple can, if they choose, use the core and build whatever they want around it.

The second thing is that they won't be using the exact, existing 440 core, because it doesn't have AltiVec, and you can't just bolt AltiVec on. It has to be part of the core itself. So whatever Apple is working on is a variant of the 440 already - while they're mucking around in the core, they could do any number of other things that suited them, like start work on a 64-bit variant when that becomes timely.
post #27 of 376
Quote:
Originally posted by wizard69
Its been awhile since I've visited IBMs information sites, but I believe that the 603 was also offered as a core. But that really doesn't matter.

The issues I see are that the 440 core would have to be extended qute a bit along with the periphrial base. Since cache is limited on the 440 this would have to be addressed also. So by the time you enlarge the cache and added an on chip interface to Apple compatible "hardware" it would seem to me that starting form the 603 would be easier. The possible gotcha here is the potential that IBM may have used a greater amount of design automation with respect to the 440. {the thought of compiling a PPC chip design on a mainframe is pretty hot}.

I think you're on to something here, since IBM has positioned themselves as being able to custom-design CPUs for customers. The automation tools are a critical part of that ability, and the 440 is a product (it's used in game consoles). Also, there's the blunt fact that the 440 core scales up better than the 603e core.

Quote:
Like I said I'm all for a SOC design, but do have to wonder if the MCM part has any reality at all. While I'm certain that two 440 plus some I/O could fit easily on one chip, I still have a problem convincing myself that this would be the avenue selected.

The principle advantage of the MCM technology is that you can get multiple chips and backside caches all talking to each other at really high speeds. If you're going to be using large number of relatively low-power cores, something like this is the only way to go about it, because if the cores can't communicate quickly and efficiently than your architecture is going to suck. I'm not sure whether the MCM tech wouldn't be cheaper than a dual-core design - up to this point, it's been used with such powerful cores and such massive caches that the final package has always been hugely expensive. It seems to be to be a sort of specialized daughtercard, but I freely admit that I'm speaking from a position of ignorance here.

Whether or not the implementation used is exactly the implementation used to glue POWER4 cores and caches together, it's going to have be something that allows for fast, low-latency, point-to-point communication between the cores and caches in order for the architecture to be effective.

This doesn't have to go into a conventional machine, either. This has blade or cluster node written all over it (among other things). The engineering would be very similar to the engineering of a notebook motherboard in either case. Ironically, it could also make a good consumer desktop - except the drop to 700MHz would be an interesting sell...
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Original music:
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Original music:
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Becca Sutlive - Iowa Fried Rock 'n Roll - now on iTMS!
post #28 of 376
Thread Starter 
this computer doesnt need redesign of core

the 440 is modular

it has an auxiliary core port

this auxiliary core is bigger than the current 440 FPU and it has altivec

the whole motherboard is based on SOC

it is similar in design to Blue Gene Compute Card except it has reduced L3 cache and SO-DIMM slot for up to 2GB DDR
post #29 of 376


That would make it the first modular design that could accomodate AltiVec as a bolt-on.

I'd really have to see how that worked without either making a complex interface or crippling AltiVec.
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Original music:
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"...within intervention's distance of the embassy." - CvB

Original music:
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Becca Sutlive - Iowa Fried Rock 'n Roll - now on iTMS!
post #30 of 376
Thread Starter 
the PPC 440 auxiliary processor interface is designed for that.

http://www-3.ibm.com/chips/techlib/t...569930064E7AA/$file/440_pb.pdf
post #31 of 376
Try again. That link's dead.
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Original music:
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post #32 of 376
I think this is the one he wanted:

440_pb.pdf

Wow... 1W at 400MHz. OK, so maybe it won't be as hot as I first thought. The sheer thought of four processors named G5 scared my testicles.
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post #33 of 376
MAYBE Apple could go all futuristic on us an introduce a quad-(cool and cheap)-proc PowerBook.

But I have a problem with two things. One, why would Apple use two dual-chip MCMs, and not one quad-chip MCM?

Next, how could the whole motherboard, for a PRO laptop, be based on SoC?

Barto
Self Indulgent Experiments keep me occupied.

rotate zmze pe vizspygmsr minus four
Self Indulgent Experiments keep me occupied.

rotate zmze pe vizspygmsr minus four
post #34 of 376
Thread Starter 
that is only 1 core though, no FPU and altivec.

however it is 1 Watt at 0.15 micron

but its also slow at 400Mhz
post #35 of 376
Thread Starter 
sory i had typo. it is one MCM with two chips that each contain two processor package together

there is nothing wrong with SOC for pro laptop. its cheap and good performance.
post #36 of 376
Quote:
Originally posted by Nr9
there is nothing wrong with SOC for pro laptop. its cheap and good performance.

Do you know the arrangement of the various MACs and controllers in relation to the chips then?

That is, are different MACs and controllers used on different chips? Obviously, there would be a DDR memory controller for each chip, but what about ethernet, USB 2, audio, WiFi etc?
Self Indulgent Experiments keep me occupied.

rotate zmze pe vizspygmsr minus four
Self Indulgent Experiments keep me occupied.

rotate zmze pe vizspygmsr minus four
post #37 of 376
Thread Starter 
the point of the 440 SOC architecture is that it is modular.

you can start with 440 core and add all the component you want

for example the 440GX already has ethernet.

the PowerBook G5 version has all the feature you wnat
post #38 of 376
I think Barto's question comes down to: Are their four MACs (that is, ethernet IDs), four FireWire controllers, four USB 2 controllers, etc.? In other words, there's nothing wrong with a system-on-a-chip design, but four systems on four chips? In a portable?

It would be more than a little unusual for a PowerBook to have or require four MACs, so it's is the sort of thing that would probably be a waste of silicon in this arrangement.

If we're going with an arrangement of two MCMs of two cores each, I'd expect the cores to be fairly minimal, except for onboard memory controllers. It seems to me that everything else - ethernet, FireWire, USB, ATA - is really better off being punted to an ASIC.

That PDF doesn't say much of anything, so I'm still not 100% satisfied that the Auxiliary Processor Interface is up to the task of handling VMX. There are DSPs that can be bolted on that way - Motorola makes them too - but nothing yet with the complexity or the bandwidth requirements of VMX (AltiVec).

It'll be really cool to see Apple start down this road (I say will because this is the road IBM and PowerPC and high-performance computing are heading down; it's only a matter of when). I'd never have guessed that the PowerBook would be the trailblazer though. That's a bit hard to swallow.
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Original music:
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Becca Sutlive - Iowa Fried Rock 'n Roll - now on iTMS!
post #39 of 376
Quote:
Originally posted by Nr9
The PowerBook G5 has 2 MCMs with 2 processor each

4 processor PowerBook G5 with modified 440 core with altivec

Do you mean that there is already a powerbook prototype in this configuration? And that this will be the next powerbook revision?
post #40 of 376
Nr9 do you have any idea of performance of this V 970?
Wll I have my G5 so I am off to get a life; apart from this post...
Wll I have my G5 so I am off to get a life; apart from this post...
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