Originally posted by stingerman
I can't seem to find the original quote, but I came across this in my past research,
In the design of pipelined processors, the hardware in each stage is optimized by restructuring logic and tuning transistor sizes to meet the cycle requirement. The tighter the delay budget, the greater the parallelism required at the gate level and the larger the transistor sizes needed, which leads to higher power.
It is clear to me, however, that "the dynamic power consumed in a chip is the sum of the power of all switching nodes."
But, in the context of the original post I made, explain to me what causes heat to be generated from an engineers perspective. I want to make sure I understand it properly.
Just how detailed an explanation do you want?
The simple version first then.
Important note) Capacitors do not themselves dissipate power (voltage and current are always out of phase). Only resistive elements can dissipate power.
For so-called dynamic power, consider the input of a (logic) gate being driven by some other circuit. First the input of the (logic) gate consists of the (control) gates of a number of transistors, which is an almost purely capacitive load. The input is controlled by a pair of transistors, one of which is connected to voltage high, and the other connected to voltage low. In the steady state one transistor is on, and the other is off.
When the logic switches the two driving transistors switch, and current flows on or off the capacitor through the newly on transistor. This current flows through the channel of the transistor, which is resistive, and hence dissipates power. However, the power dissipated is not directly controlled by the resistance, but by the capacitance, and the voltage range, which control the total charge moved around.
There is another element of dynamic power dissipated, which is becoming more important at shorter sizes, which is the current that flows through the two transistors whilst both are switching and there is a direct resistive path from high voltage to low voltage. It so happens that this current is approxiamtely proportional to the gate capacitances of the transistors, and is usually approximated by a fudge factor correction to the capacitance based calculation.
On top of this, and related to the original post, is that the voltage you need to use to make the transistors work properly depends on the size of the transistors, a shorter gate length means a lower voltage is required to achieve the electric field under the gate which will give velocity saturation of the carriers. This is complicated by the fact that the voltage must also be high enough to cope with the variation in threshold voltage of transistors (the input voltage at which the transistor switches from on to off or vice-versa) and current processes run at much higher voltages than would otherwise be necessary because there is considerable variation in threshold voltage accross a wafer or even a chip.
The original post mentioned that reducing the size of the transistors would increase the channel resistance, and hence require a higher voltage, leading to no reduction in power dissipation, but this doesn't take into account the simultaneous scaling of the capacitances etc., nor the fact that the resistance doesn't control the total charge moved around per state change, but just the current, (which controls the speed of switching). So that reducing the process size does reduce the power dissipated.
Much more interesting at very short gate lengths and thin gate dielectrics are the leakage currents which give rise to both dynamic and static power dissipation, and controlling these is probably the most difficult part of developing new processes.
The more complex version isn't really suited to this board, but ask if you want it.