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Will Apple move to the POWER 5 instead of PPC? - Page 2

post #41 of 122
Quote:
Originally posted by T'hain Esh Kelch
Steve also said no Photo iPod..

When? Where? And who cares, anyway, since there have never been any significant technical obstacles to putting a color screen on an iPod? (For the record, in his original introduction of the iPod, when he explained the name, he was quite clear that Apple had intentionally called it a "container" rather than narrowly restricting it to music. Music is just the "killer app.")

Besides, this isn't something Steve has or hasn't said. This is something Motorola and IBM and Apple engineers have said. There is simply no need for a double-width AltiVec 2. There is no indication that it would faster, and in fact it might be slower. There is no technical analysis that I've seen where a 256-bit-wide AltiVec unit comes out ahead, especially not on a design like the 970 that already takes a hit from having to burn a cycle to synchronize all the copies it keeps of its register sets.

The 970 has two full-featured, blazing fast 64-bit FPUs. Every PowerMac has two 970s. That's as close to an "AltiVec 2" as you're going to get for a very, very long time. And to answer a previous post of yours, it makes no sense to roll out a new version just as people are warming up to the first one. This isn't an accessory like an iPod. It's hardware that people have to spend long hours learning, and optimizing for, and investing in. In system software and hardware, change is bad for adoption. It's viewed as pulling the rug out from under your developers. Look at the last big run-up in video cards: New technology came so fast and so furious that hardly any games adopted any of it. So the GPU vendors would show these gorgeous demos, and then the next year's crop of games would look a lot like the previous years', with higher framerates a few minor enhancements. It's only now that a common set of functions have been defined in OpenGL and DirectX, and implemented broadly, that we're seeing advanced support for programmable textures and other capabilities that had been neglected for the previous three or four years. Or, look at all the attempts at vector engines on the x86 side, which have simply resulted in hardly any of them being supported at all (most of the support consists of using SSE as an FPU, since the x86's onboard FPU sucks).

Apple, IBM and Motorola did AltiVec once. They got it right the first time. I have seen exactly zero pressure from those people who actually use it for a version 2.0. For comparison, the PowerPC spec, approved in 1994, is also still on version 1. It's only ever been tweaked here and there, and somehow that's not a problem.
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post #42 of 122
G6 - More POWER on the way


OSnews seems to agree with Brendon's speculation about Apple getting a POWER 5 "lite" from IBM

Quote:
All in all, the POWER5 is a very impressive processor, especially given that it is implemented in a previous-generation (130nm) silicon process and IBM use a deliberately conservative design process.

If rumours are to believed, IBM are working on a desktop version of this CPU. The question is can IBM translate these sorts of performance gains to the desktop? We can't expect performance like POWER5 but what can we expect?


... The CPU will most likely be made using a 90nm process in a less conservative manner than the POWER5 so it will run faster and cooler. Quite how fast it will be able to run is open to question and I think it's fairly likely IBM will go the same route as AMD in their dual core plans and not clock the processor as high as possible to keep power consumption within reasonable limits. This will not be easy as POWER5 consumes 160 Watts at 1.8GHz (power consumption isn't much of an issue at the high end).

One possibility is to use the same technique the POWER5 already uses which is to constantly adjust the clock frequency to keep heat output down. This technique is becoming popular with Transmeta and Intel doing or planning to do the same.

Another possibility would be to use a technique Intel plan to use for the next Itanium "Montecito," which includes two peltiers in the heat sink. Peltiers actually consume quite a bit of power themselves but reducing the CPU temperature reduces transistor leakage, this lowers the power consumed by the CPU itself allowing boosts in clock frequency which might not otherwise be possible.

Montecito is expected to consume 100 Watts but its heat sink requires a further 75 watts. The end effect is overall power consumption does not change (it may even go up) as part if moved to the heat sink but the CPU itself does not get so hot when working. AMD have filed a patent on an on-chip peltier so they're evidently considering similar technology.

I don't know if the 9x0 will be so hot as to require such aggressive cooling but things are heading that way. "Power density" is becoming a problem and will seemingly only get worse in the future. Power density is the heat generated in a specific area; as CPUs get ever smaller the heat is generated in a smaller area and thus the unit becomes progressively more difficult to cool. The 970FX used in Apple's PowerMacs actually uses less power than the previous 970 but liquid cooling was added because of the higher power density.
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post #43 of 122
pffffft
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post #44 of 122
Thread Starter 
BUMP!

Interesting article:

http://www.macworld.co.uk/news/index...S&NewsID=10439

Maybe it will happen.
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post #45 of 122
Quote:
Originally posted by onlooker
pffffft

If you must fart in public, please excuse yourself.
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post #46 of 122
Thread Starter 
Quote:
Originally posted by cubist
And how much market is there for $10K+ Macs anyway? Weren't they "the computer for the rest of us"?

Believe it or not I thought that this would be why IBM would be interested in the idea, except from the other way around. I have no idea what the size of the POWER5 market is except I wold guess that the Mac market is many times larger. It appears that the cost of the POWER5 chips is mostly in R&D costs, because the manufacturing process is not cutting edge, and I would assume chosen because it is well understood and therefore more rubust. By selling these to Apple the R&D costs per unit go down quite allot. If IBM is selling these POWER5s in the 100,000s per year and they could sell them to Apple in the 1,000,000s pe year, the expanded market and the significantly lower R&D costs per unit would make good economic sence for IBM. Read IBM could sell them to Apple and to themselves for a much lower cost. As far as Altivec goes, I don't have an answer for that. Or maybe we are just talking servers. Or, what if there were to be a processor that because of its other technologies pretty much nullified Altivec, sorry Altivec fans, but then Apple would then not have to promote using a special processing unit, which may not be done just for the economics of time to port. Maybe this is what core media is all about, just let Apple write the libraries and other companies don't have to worry about wheather Altiec is being used or not. At some point Altivec because it cannot evolve at a fast pace will fall behind and Apple should be prepared, maybe we are seeing the beginning of that time. Maybe the transition is at foot.
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post #47 of 122
Quote:
Originally posted by Brendon
Or, what if there were to be a processor that because of its other technologies pretty much nullified Altivec, sorry Altivec fans, but then Apple would then not have to promote using a special processing unit, which may not be done just for the economics of time to port. Maybe this is what core media is all about, just let Apple write the libraries and other companies don't have to worry about wheather Altiec is being used or not. At some point Altivec because it cannot evolve at a fast pace will fall behind and Apple should be prepared, maybe we are seeing the beginning of that time. Maybe the transition is at foot.


You are spewing nonsense here. The POWER5 currently shipping in IBM product was designed for big iron uses, not for Apple. Apple simply could not use the POWER5 as it is and the reason has nothing to do with AltiVec. There is no "move to POWER5 instead of PowerPC". They will move to POWER5 when it is a PowerPC.

When they bring the POWER5 technology out in a "lite" version they will add AltiVec, just like they did for the 970. There is nothing about it not evolving at a fast pace -- you've only seen one processor (well, two if you count the 970/970FX) with it from IBM and you are making predictions about how they can't evolve it? Take it from me, there is no problem adding it to the POWER5 and making improvements to VMX is no different than making improvements to the other parts of the processor if the improvements are requested by their customer(s).

The Core media initiatives are created by Apple as a way to provide services written by Apple to application developers that take direct advantage of any and all hardware advances, without application developers having to be aware of it. AltiVec can be used for many things beyond the scope of the Core services, however, and so it retains substantial value all on its own.
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post #48 of 122
The OSnews article acknowledges "there is pretty much zero public data available on the project..." In other words, its fantasy.

As for Altivec 2, show me where the clamor is for an improved Altivec implementation? There is none and the dream of Altivec 2 is fueled by the same lust that drives folks to buy amps that "go to 11."

So here's an extrordinarily bold GUARANTEE... IBM will make a successor to the 970. The successor will draw upon designs from other IBM chips. The bus and clock speed will be higher. It will more thermally efficient. It will be fabbed at a smaller size. This chip will appear sometime in the future.
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post #49 of 122
Since were talking about if Apple will move to the POWER 5......</sarcasm>
I'm hoping that the upcoming xbox, Playstation, Cube, etc. all use some implementation of Altvec/VMX/Velocity Engine, in their PPC cpu's. This increased programing knowledge base would no doubt trickle over to Apple software over time.

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post #50 of 122
Thread Starter 
Quote:
Originally posted by Programmer
You are spewing nonsense here. The POWER5 currently shipping in IBM product was designed for big iron uses, not for Apple. Apple simply could not use the POWER5 as it is and the reason has nothing to do with AltiVec. There is no "move to POWER5 instead of PowerPC". They will move to POWER5 when it is a PowerPC.

When they bring the POWER5 technology out in a "lite" version they will add AltiVec, just like they did for the 970. There is nothing about it not evolving at a fast pace -- you've only seen one processor (well, two if you count the 970/970FX) with it from IBM and you are making predictions about how they can't evolve it? Take it from me, there is no problem adding it to the POWER5 and making improvements to VMX is no different than making improvements to the other parts of the processor if the improvements are requested by their customer(s).

The Core media initiatives are created by Apple as a way to provide services written by Apple to application developers that take direct advantage of any and all hardware advances, without application developers having to be aware of it. AltiVec can be used for many things beyond the scope of the Core services, however, and so it retains substantial value all on its own.

Spewing? A little graphic. I spew therefore I am. So I am spewing my opinions and speculations on a rumors board. It is a rumors forum. The future hardware forum is steeped in fact, I can't look at a single thread and say wow that is pure speculation. I have said that Altivec is difficult to evolve due to the fact argued by you and others that big changes to Altivec hamper its adoption, and could make life difficult for those that utilize it. By having to support Altivec new and Altivec old. So following that logic I would assume that Apple along with IBM would like to make Altivec like instructions part of the processor core. This appears t be what IBM is doing, in that they add special capabilties to parts of the execution units instead of having special unit like Altivec. Take for example the discussion about the design of the POWER6 processor, they are adding more stuff to be implemented in hardware, and not in a special execution unit like Altivec/VMX, instead of software. Will IBM continue to grow the PPC line yes, but that has little to do with wheather Apple chooses to use them. Again let's look at the adoption rate of Altivec, at some point it may be easier to move away from those issues. How well does the compilier work with making code work well with Altivec. How many people have the time to learn about when and how to use Altivec. As I see it Altivec bought Apple lead time at being able to encode DVDs cheaply. There are uses for it in products like Motion, FCP, Photograph and the like, but at some point just adding some extra capabilities to the FPU along with the fact that processors are so much faster than they were when we needed the 733MHz G4 to burn DVDs, when will those advantages not be so great. The point is everything evolves. Altivec goes back a long time with little evolution, great for adoption, but is that adoption rate, the rate that customers can see benefit enough to use the tools and to continue to use the tool, enough for Apple to continue to back it. Altivec is great for some things, but the rest of the processor is getting faster still, and IBM seems to like to add capabilities to the core and not rely on special processing units like VMX. IBM said from the beginning that they had no plans to use Altivec, it is there because Apple wants it there. I think that IBM would rather add special capabilities to the usual processing units that are easier to incorporate into the compilier and easier for the programmers to use. Just a different way of slicing the Apple, if you will.

PS I just got an amp that does go to 11, love it, really. Much better than the 10 version.
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post #51 of 122
Quote:
Originally posted by Ompus
As for Altivec 2, show me where the clamor is for an improved Altivec implementation? There is none and the dream of Altivec 2 is fueled by the same lust that drives folks to buy amps that "go to 11."

At least in my case, it is not a clamor for an improved Altvec implementation, rather it is rejection of the idea that AltVec can't be improved significantly. Some of the reasoning I see presented in this forum surprises me to no end as I expect that some of the people are technically literate here. The number one thing that people have to realize is that hardware that doesn't evolve dies. It is like TI saying that their last DSP chip is the best that ever will be and dropping all R&D for anything new. The fact that IBM, Motorola/Freescale & Apple did a good job with AltVec doesn't elminate the fact that technology moves forward.
Quote:

So here's an extrordinarily bold GUARANTEE... IBM will make a successor to the 970. The successor will draw upon designs from other IBM chips. The bus and clock speed will be higher. It will more thermally efficient. It will be fabbed at a smaller size. This chip will appear sometime in the future.

See you do understand!!!!
Others see ways obstructing the march forward, you do seem to realize that there is much yet that can come to market.

Thanks
Dave
post #52 of 122
Quote:
Originally posted by Brendon
I have said that Altivec is difficult to evolve due to the fact argued by you and others that big changes to Altivec hamper its adoption, and could make life difficult for those that utilize it.

This subject certainly is frequently misunderstood. What I argue against is changing the instruction set architecture unless there is huge benefit to be had. This applies to the basic PowerPC ISA just as much as it applies to the VMX extension to it. VMX is no more difficult to evolve than the rest of the ISA. There are all sorts of opportunities to improve on the current implementation in all areas, including VMX. And VMX is part of the core, it was a change made to the PowerPC ISA back when the G4 was introduced. It is just as much part of the core as the FPU is.

Quote:
Again let's look at the adoption rate of Altivec, at some point it may be easier to move away from those issues. How well does the compilier work with making code work well with Altivec. How many people have the time to learn about when and how to use Altivec.

Come back again in 2 years and you will see much much wider adoption of VMX. You'll also see better tools for taking advantage of it more easily. I'm also hopeful that we'll see better implementations, much like the G4's implementation improved from the 7400 to the 7450. This is actually more likely than improvements to, say, the integer multiplier since IBM has evidently not improved that unit in the POWER4->5 transition.

It will be interesting to see what IBM does in the POWER6. That will apparently be an all-new microarchitecture. I would not be at all surprised to see IBM build VMX into that, even for their servers, simply because the marginal cost of adding it is relatively slight and the demand for it is growing.

Quote:
Altivec is great for some things, but the rest of the processor is getting faster still, and IBM seems to like to add capabilities to the core and not rely on special processing units like VMX. IBM said from the beginning that they had no plans to use Altivec, it is there because Apple wants it there. I think that IBM would rather add special capabilities to the usual processing units that are easier to incorporate into the compilier and easier for the programmers to use. [/B]

That was IBM's original stance, but things change. IBM will deliver what its customers want, and VMX is on that list. VMX isn't mutually exclusive with those other capabilities you're talking about -- we will likely see more specialized units in system-on-chip designs, but they usually will not take the form of modifications to the ISA. And most of them will be exposed via an operating system API as opposed to having direct hardware access.
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post #53 of 122
Quote:
Originally posted by wizard69
At least in my case, it is not a clamor for an improved Altvec implementation, rather it is rejection of the idea that AltVec can't be improved significantly. Some of the reasoning I see presented in this forum surprises me to no end as I expect that some of the people are technically literate here. The number one thing that people have to realize is that hardware that doesn't evolve dies. It is like TI saying that their last DSP chip is the best that ever will be and dropping all R&D for anything new. The fact that IBM, Motorola/Freescale & Apple did a good job with AltVec doesn't elminate the fact that technology moves forward.

And sometimes hardware that does evolve dies -- if the direction is wrong then it wasn't a good evolution. This has been demonstrated repeatedly over the years, including a painful example or two by IBM.

There is plenty of opportunity for improvement in AltiVec (and PowerPC in general) without changing the ISA. IBM said exactly this when they did a study to determine whether to build the POWER4, and the result was a compatible architecture in POWER4, POWER5 and (according to their plans) POWER6 & POWER7. It is pretty much the whole point of http://power.org/.


This is one case where an automotive analogy works really well: to build faster cars, more fuel efficient cars, more capacious cars, etc. there is no need to change the basic driver interface: steering wheel, gas, brake, shift lever, and (maybe) a clutch. Having to deal with the difference between auto and manual causes enough trouble, imagine if every vehicle added a new kind of pedal or lever? And remember that you're more like a valet than a normal driver -- you need to be able to hop into any car and drive immediately. Now go and look at the diversity of vehicles available with this same basic interface. The advantages of maintaining the interface are tremendous, and there is still plenty of potential to be exploited.
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post #54 of 122
Quote:
Originally posted by Programmer
This is one case where an automotive analogy works really well: to build faster cars, more fuel efficient cars, more capacious cars, etc. there is no need to change the basic driver interface: steering wheel, gas, brake, shift lever, and (maybe) a clutch. Having to deal with the difference between auto and manual causes enough trouble, imagine if every vehicle added a new kind of pedal or lever? And remember that you're more like a valet than a normal driver -- you need to be able to hop into any car and drive immediately. Now go and look at the diversity of vehicles available with this same basic interface. The advantages of maintaining the interface are tremendous, and there is still plenty of potential to be exploited.

This is the whole point there is much room to improve AltVec without changing what the existing code base sees. You can add a tubo charge to a car an many people will never know its true potential, but the user that knows it is there can exploit it to the maxium. The addition does not change the interface at all for the normal user.

Likewise Atlvec can be extended to improve its performance. Like a turbo some of those improvements might give a user a boost that they are not aware of. For others they can milk (program) even more performance out of the unit.

I think the bigger question is will AltVec even be supported on newer hardware as we know it today. Apple does have options as it moves forward, maybe we will see vector operations handled in a seperate execution unit.

Dave
post #55 of 122
Thread Starter 
Quote:
Originally posted by Programmer
And sometimes hardware that does evolve dies -- if the direction is wrong then it wasn't a good evolution. This has been demonstrated repeatedly over the years, including a painful example or two by IBM.

There is plenty of opportunity for improvement in AltiVec (and PowerPC in general) without changing the ISA. IBM said exactly this when they did a study to determine whether to build the POWER4, and the result was a compatible architecture in POWER4, POWER5 and (according to their plans) POWER6 & POWER7. It is pretty much the whole point of http://power.org/.


This is one case where an automotive analogy works really well: to build faster cars, more fuel efficient cars, more capacious cars, etc. there is no need to change the basic driver interface: steering wheel, gas, brake, shift lever, and (maybe) a clutch. Having to deal with the difference between auto and manual causes enough trouble, imagine if every vehicle added a new kind of pedal or lever? And remember that you're more like a valet than a normal driver -- you need to be able to hop into any car and drive immediately. Now go and look at the diversity of vehicles available with this same basic interface. The advantages of maintaining the interface are tremendous, and there is still plenty of potential to be exploited.

OK the point for discussion purposes only, is Altivec or no. Let's assume no. The assumption could be based on assumptions that maybe 15% of the programs for the Mac use Altivec, and out of those that do use it only 25% fully exploit most of the capabilities of Altivec. If that is anywhere close to the case then Apple maybe better served by asking IBM to alter the FPU, and save the transistors and the development costs. Basically take the few instructions that are used the most and keep those and lose the rest. Now it appears to me that the compilier is easier to write so that it takes advantage of the extra capabilities of the FPU and or Int.U and more people will be able to benefit from those capabilities, on a more straight forward way. No more special Altivec code and then the rest of the code. To me it appears that Apple could be better served by having more people to work on the whole compilier rather than supporting and improving tools for a unit that sees very little use in the market as a whole. I know that the adoption rate will grow but will that rate keep pace with the growth of developers coming to the Mac or will Altivec be marginalized further? When the economics of coding choice meet the economics of tools and support of those tools. At that time maybe the POWER5 may look very good in that, the manufacturing process is very robust, they probabily get high yields. All of the redundentcy may not be needed making the processors made for Apple to be indenticle to the POWER5 except for the redundency, making those easier to make and cheaper. Yields may also play a key role as well in that if Wall Street is to be believed and Apple comes out with a flash memory player and the amount of people caught in the halo effect grows or continues to grow, Apple could easily double the amount of shipping Macs, in one year, '05. Will IBM be able to keep up with that growth? Maybe they could if the processors used were spread out over a larger product line, one that includes the POWER5. I don't know anything about the yields of the POWER line but that along with the fact that the POWER line is kicking some serious assumptions aside, may be another reason for Apple to put these in the desktop line thus freeing up more PPC for the consumer lines.
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post #56 of 122
Quote:
Originally posted by wizard69
This is the whole point there is much room to improve AltVec without changing what the existing code base sees. You can add a tubo charge to a car an many people will never know its true potential, but the user that knows it is there can exploit it to the maxium. The addition does not change the interface at all for the normal user.

What's this? We agree? Do I hear hell freezing over?

Quote:
I think the bigger question is will AltVec even be supported on newer hardware as we know it today. Apple does have options as it moves forward, maybe we will see vector operations handled in a seperate execution unit.

First of all, what do you mean by "a seperate execution unit"? Right now AltiVec is a pair of seperate execution units -- seperate from the load/store, integer, and floating point execution units. I suspect you mean as a seperate core, like Cell is rumoured to be. In this case I agree but they don't have to be mutually exclusive: the presence of specialized vector cores doesn't obviate the need for vector execution units in the general purpose core any more than specialized floating point cores would obviate the need in the general purpose core.

VMX will be supported, mark my words.
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post #57 of 122
Quote:
Originally posted by Brendon
OK the point for discussion purposes only, is Altivec or no. Let's assume no. The assumption could be based on assumptions that maybe 15% of the programs for the Mac use Altivec, and out of those that do use it only 25% fully exploit most of the capabilities of Altivec.

Only that many use it directly, but many use libraries and OS functionality that leverages AltiVec. Some of this functionality would make sense to move onto new kinds of hardware but some doesn't.

Quote:
If that is anywhere close to the case then Apple maybe better served by asking IBM to alter the FPU, and save the transistors and the development costs.

I think Apple has proven that AltiVec is more than valuable enough to retain. The same number of transistors added to the FP or integer capabilities of the basic PowerPC core would have much less return on investment.

Quote:
Basically take the few instructions that are used the most and keep those and lose the rest.

Either you lose 'em all or you keep 'em all. The marginal savings by removing selected instructions is virtually zero, and the cost is breaking compatibility.

Quote:
Now it appears to me that the compilier is easier to write so that it takes advantage of the extra capabilities of the FPU and or Int.U and more people will be able to benefit from those capabilities, on a more straight forward way. No more special Altivec code and then the rest of the code. To me it appears that Apple could be better served by having more people to work on the whole compilier rather than supporting and improving tools for a unit that sees very little use in the market as a whole.

Vectorization support is coming in the next GCC, and Apple has optimized a great deal of its support code to use AltiVec already. Going back now would be pointless, and in the future this kind of SIMD hardware is going to be more common, not less. That will further improve the tools and increase the amount of coding using it.

There is no problem adding VMX to the POWER5 (and future) designs. They did it with POWER4 without causing trouble, and at the very least POWER5 can adopt the VMX unit from the POWER4 (but will likely improve on it). There are much bigger factors that prevent Apple from using POWER5 as it is, so much so that the lack of VMX is pretty much inconsequential. In the process of addressing those issues, adding in VMX isn't an issue.
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post #58 of 122
Thread Starter 
Quote:
Originally posted by Programmer
Only that many use it directly, but many use libraries and OS functionality that leverages AltiVec. Some of this functionality would make sense to move onto new kinds of hardware but some doesn't.

I think Apple has proven that AltiVec is more than valuable enough to retain. The same number of transistors added to the FP or integer capabilities of the basic PowerPC core would have much less return on investment.

Either you lose 'em all or you keep 'em all. The marginal savings by removing selected instructions is virtually zero, and the cost is breaking compatibility.

Vectorization support is coming in the next GCC, and Apple has optimized a great deal of its support code to use AltiVec already. Going back now would be pointless, and in the future this kind of SIMD hardware is going to be more common, not less. That will further improve the tools and increase the amount of coding using it.

There is no problem adding VMX to the POWER5 (and future) designs. They did it with POWER4 without causing trouble, and at the very least POWER5 can adopt the VMX unit from the POWER4 (but will likely improve on it). There are much bigger factors that prevent Apple from using POWER5 as it is, so much so that the lack of VMX is pretty much inconsequential. In the process of addressing those issues, adding in VMX isn't an issue.

Thanks for helping me with my adoption numbers, I was sweating all of those assumptions.

Are you sure about "Either you lose 'em all or you keep 'em all." statement, that seems strange to me. But if you are correct your point of all or nothing would mean a lock for VMX.

I didn't know vectorization was coming to the GCC, I wonder if this will boost adoption or splinter the tools support, I really have no idea.

Could you please elaborate on the whys of why Apple would have problems and factors with using the POWER5 with and without VMX. Assume that I know nothing. Would heat be one of these issues? Price? IBM being a hording bastion? Apple waiting for POWER11?
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post #59 of 122
Thread Starter 
Quote:
Originally posted by Programmer

There is no problem adding VMX to the POWER5 (and future) designs. They did it with POWER4 without causing trouble, and at the very least POWER5 can adopt the VMX unit from the POWER4 (but will likely improve on it). There are much bigger factors that prevent Apple from using POWER5 as it is, so much so that the lack of VMX is pretty much inconsequential. In the process of addressing those issues, adding in VMX isn't an issue.

VMX or not the POWER5 real world numbers are right up there with some theoretical numbers. With and without VMX, if you know what I mean.
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post #60 of 122
Quote:
Originally posted by Brendon
Thanks for helping me with my adoption numbers, I was sweating all of those assumptions.

I don't have any hard numbers, but those sound like a reasonable guess. The fallacy of that kind of metric, however, is that most of the 75% that don't use AltiVec don't need AltiVec.

Quote:
Are you sure about "Either you lose 'em all or you keep 'em all." statement, that seems strange to me. But if you are correct your point of all or nothing would mean a lock for VMX.

I argue for leaving the VMX instruction set as-is so that existing software that uses it will continue to operate correctly. If you remove instructions, some software will break. If you add some instructions and developers use those then you've fragmented your installed base. The major cost of VMX is that there are execution units & pipelines for it, and the 32 128-bit registers. As soon as you have 1 VMX instruction you need those things, so you might as well go the whole 9 yards.

If legacy software wasn't an issue (i.e. you're not Apple) then you might make changes to the ISA, depending on your anticipated audience. This is the most likely reason for VMX2 to show up -- if IBM decides to add it to POWER6 (or some other member of power.org decides they want it in another processor) they have no legacy and thus are free to introduce additional instructions and changes, regardless of Apple's legacy requirements. In the case of IBM doing it, this might then trickle down to a PPC990 or something then Apple machines would end up with it. So far I have seen no sign of IBM making changes to the VMX ISA, however.

Quote:
I didn't know vectorization was coming to the GCC, I wonder if this will boost adoption or splinter the tools support, I really have no idea.

Even more telling is that IBM is adding it to their POWER compiler. That ought to be a clue of things to come in the future.

Quote:
Could you please elaborate on the whys of why Apple would have problems and factors with using the POWER5 with and without VMX. Assume that I know nothing. Would heat be one of these issues? Price? IBM being a hording bastion? Apple waiting for POWER11?

The cache architecture, the MCM physical organization, the size of the cache, the memory architecture, that the chip is designed for reliability over density/yield and the costs that result from that, etc. There are a lot of things that go into chip design that don't show up from an ISA point of view. These things just aren't condusive to the kinds of machines and the price point that Apple targets.
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post #61 of 122
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.

You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
The PPC 970 chip and derived are the future of Apple.
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache
post #62 of 122
Quote:
Originally posted by Powerdoc
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.

You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
The PPC 970 chip and derived are the future of Apple.
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache

.
.
.
SMT
on-chip memory controller
system-on-chip I/O features
.
.
.
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post #63 of 122
Thread Starter 
Quote:
Originally posted by Powerdoc
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.

You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.
The PPC 970 chip and derived are the future of Apple.
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache

And

Quote:
Originally posted by Programmer
.
.
.
SMT
on-chip memory controller
system-on-chip I/O features
.
.
.

One point that I remember is that the PPC would be the area for the cutting edge stuff, and the things that had been perfected there would then migrate to the POWER series. I quote "The POWER series will always lag the PPC series because they IBM will never ship someting that is not mature in hte POWER series." NOTE that all of the above mentioned improvements are to be found in the POWER5, OK maybe not S-O-C I/O features, but the rest I'm pretty sure of. Maybe it is the other way around the PPC will inherit from the POWER series.
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post #64 of 122
Quote:
Originally posted by Powerdoc
This is a recurrent thread, many posters like The programmer have emphasized this : the power line is much more than a dual core PPC line. It's a server chip, with features especially made for such tasks.

True but those server features do not detract from its usefullness to Apple. I would have to think at some point that adding the little bit extra to Power5 that Apple needs for its machines would in the end be a win for everybody.
Quote:

You will never see a power chip in an Apple desktop. It cost way too much, it will not improve the performances.

This I agree with, but on the other hand it shouldn't be to difficult to derive a new PPC chip from Power5 just like they did for the 970 and Power4. It makes more sense from an engineering point of view than maintaining an old architecture. Not that Power4 / 970xx is old just that development effort would make more sense on hardware expected to be around for a few years.

I think you also underestimate performance improvements. From the system point of view I can see OS/X making real good use of Power5 derived hardware.
Quote:
The PPC 970 chip and derived are the future of Apple.

From the day in debuted I have been convinced that that is not the case. I see the 970 series as a stop gap measure that Apple pursued due to basically being desperate. If IBM had long term intentions with respect to the 970 series they would have made some design decisions that would make it usefull and saleable to markets outside of Apple.
Quote:
There is many improvement to do with this chip :
- going dual core and multicore
- improving the core without changing the ISA. For example Altivec can be optimised, like Mot did with the 7450 compared to the 7400. The core can be also more pipelined ...
- greater L1 and L2 cache

True all of these improvements can help but then agian you can get the same results by tacking a Vector unit onto a Power5 and optimising the chip for 90nm processing. In the end does it really make sense to back port hardware you already have working in Power5, especially considering that a 90nm Power5 derived core will untimately still be smaller than the dual core hardware Intel and AMD will be shipping in large quanities next year. That Power5 derived core would only have to be optimized/altered in a few places for desktop use.

That is one point of view. The reality is that IBM has so many projects going on right now, with respect to Power and PPC, that it is hard to tell what Apple will get in the future. If Cell or the MS driven hardware is at all successfull and delivers on promise we could have some surprises from Apple. The reality is Apple needs hardware that supports multithreading/multiprocessing cheaply. An approach that gets lots of core on chip is likely to be the winnning approach.

Dave
post #65 of 122
Quote:
Originally posted by Programmer
What's this? We agree? Do I hear hell freezing over?

Well not exactly as I consider adding instruction that do not impact the current ISA fair game. I fully understand that there is much that can be done within the current instruction set for Vector operations. Everyone seems to agree on that as frankly not much has changed with AltVec in a long time. The point is that I also see enhanced istructions as being an important step forward also.
Quote:



First of all, what do you mean by "a seperate execution unit"? Right now AltiVec is a pair of seperate execution units -- seperate from the load/store, integer, and floating point execution units. I suspect you mean as a seperate core, like Cell is rumoured to be.

That is exactly what I was thinking about and my lack of preciseness is regretted. The point is that if Cell becomes a run away succcess (Personally I highly doubt that) Apple may be forced to make changes. One of those changes would be to adopt Chips with many CORES, which is difficult to do if everyone of them has a big vector unit attached.
Quote:
In this case I agree but they don't have to be mutually exclusive: the presence of specialized vector cores doesn't obviate the need for vector execution units in the general purpose core any more than specialized floating point cores would obviate the need in the general purpose core.

In a world of quick and light cores, the current arraingement with AltVec would have to disappear. If you need 4 to 8 real cores on a chip you won't be able to do that with an extra execution unit on each one.
Quote:

VMX will be supported, mark my words.

Yes it will probally be supported mostly due to Appl having so much code invested in it. The problem is does this become a ball and chain around the flagship product? Frankly I don't know alot about the MS or Sony approaches other than the heavy reliance upon apparently many cores. If however either company can start to deliver a low cost truely high performance workstation to the market Apple will have to take notice. Imagine a workstation with 3 to 8 PPC cores plus whatever vector facilites they decide to implement, sound earth shaking to me.

Dave
post #66 of 122
Quote:
Originally posted by wizard69
[B]True but those server features do not detract from its usefullness to Apple. I would have to think at some point that adding the little bit extra to Power5 that Apple needs for its machines would in the end be a win for everybody.

And they could very well do it, in fact I think they will include VMX in some future chip. I don't buy the argument that VMX is not useful in servers. They must see that Apple puts it to good use and there are some areas in computational servers (as opposed to file/print servers) where VMX would help IBM (look at what Altivec does for BLAST for instance, biotechnology is an area IBM are investing in heavily).

I think it is a matter of time. There seemed to be a thawing in IBM's attitude to VMX a few years ago. Power 4 was a massive 5 year project started before the first release of the G4 series of designs. Power 5 was started well before Power 4 was finished so it might have had many elements of the design nailed down before the change of attitude to VMX. Power 6 might have started late enough to have it included in the design.
post #67 of 122
hi there,
the discussion of adding altivec or not is completely bogus.
soon we will see chips with a billion transistors. altivec is composed of a couple of million transistors. the question right now is how to exploit the performance out of so many transistors. answers to this include SMT, multiple cores, IMC, SIMD units, cache, super scalarity and OOOE.
second point. the rumored PPC 970MP looks a lot like Power4. It's a dual core chip, with more or less identical cores to Power4. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size and process tech.
a proposed Power5 variant will be very very close to Power5 too. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size, process tech and possibly some of the self-healing redundancy stuff.
about altivec 2. i heard quite some whining that altivec does not support double precision fps. while it is right that altivec is a very solid design, saying there is no room for improvement in the ISA is dumb. as long as a improved altivec 2 is compatible with altivec there is no problem at all. the fragmentation of instruction sets has been a reality for software developers forever. there is no stability. in the mac space examples for this are 68k->PPC and G3->G4. as a software developer you are accustomed to change. In Java with every version new capabilties are added and other are being deprecated and ultimately become unsupported.
of course optimizations in implementation will improve performance, but this cannot be the sole way of improvement.
as programmer pointed out earlier autovectorization is coming to gcc and Apple ships several libraries with common math functions, etc with OS X. this means that the programmer is liberated from knowing the instruction set. as long as the semantics are defined those libraries or the compiler will generate quite good code.
i want to open another topic. we are moving to multiple cores. how are we going to feed the beasts? currently one processor sits on one bus. i suppose performance will degrade noticeably when multiple cores share a bus. isn't the time ripe for NUMA in a pc?
thanks for your comments.
bye cocoa tree
post #68 of 122
Hi cocoa;

While I don't totally disagree with you I do have some comments.

Quote:
Originally posted by cocoa tree
hi there,
the discussion of adding altivec or not is completely bogus.
soon we will see chips with a billion transistors. altivec is composed of a couple of million transistors. the question right now is how to exploit the performance out of so many transistors. answers to this include SMT, multiple cores, IMC, SIMD units, cache, super scalarity and OOOE.
second point. the rumored PPC 970MP looks a lot like Power4. It's a dual core chip, with more or less identical cores to Power4. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size and process tech.
a proposed Power5 variant will be very very close to Power5 too. the sole difference is SMP support, hypervisor support, the memory hierarchy & FSB, feature size, process tech and possibly some of the self-healing redundancy stuff.

As you mentioned above we are coming into an age where we will have a huge number of transistors available on a die. Why bother with a version of Power 5 that deletes SMP, hypervisor or anything else that might be usefull on the desk top? As to SMP it is glaringly obvious where the industry is going there, I suspect in a couple of years it will be difficult to even buy a processor with less than 2 cores. The rest of Power 5 is modular enough that a new memory controller should not be an issue if needed. Even that I question as the current Power5 memory arrangement is implementable on a desktop PC.
Quote:
about altivec 2. i heard quite some whining that altivec does not support double precision fps. while it is right that altivec is a very solid design, saying there is no room for improvement in the ISA is dumb. as long as a improved altivec 2 is compatible with altivec there is no problem at all. the fragmentation of instruction sets has been a reality for software developers forever. there is no stability. in the mac space examples for this are 68k->PPC and G3->G4. as a software developer you are accustomed to change. In Java with every version new capabilties are added and other are being deprecated and ultimately become unsupported.

AltVec and a redevelopment into AltVec2 should not be a problem as you pointed out. For those not interested or not able to take advantage of new performance features in AltVec2, they can just code for AltVec. There is much that can be done to improve AltVec, both for the general case and specific applications.

As to instruction set expansions what I'd love to see is an on board logic array that would allow one to build and execute application specific logic. One of my Linux mags has an interesting article on this, it would be neat to have such an array available as another core on the die.
Quote:
of course optimizations in implementation will improve performance, but this cannot be the sole way of improvement.
as programmer pointed out earlier autovectorization is coming to gcc and Apple ships several libraries with common math functions, etc with OS X. this means that the programmer is liberated from knowing the instruction set. as long as the semantics are defined those libraries or the compiler will generate quite good code.

While some of the libraries are excellent the idea that a compiler will generate good vector code is still to be proven. Ultimate exploitation of this hardware requires manual intervention at this time.
Quote:
i want to open another topic. we are moving to multiple cores. how are we going to feed the beasts? currently one processor sits on one bus. i suppose performance will degrade noticeably when multiple cores share a bus. isn't the time ripe for NUMA in a pc?
thanks for your comments.
bye cocoa tree

As to on chip SMP you have a good question, I suspect that FOR MOST APPLICATIONS it will be a win. You will take a hit though if both threads are nearly saturating the memory bus. The question is how often does this happen, like all things PC related this is really user related.

As can be seen in the AMD world, NUMA does have its advantages. They will soon have dual core chips widely available so answers will soon be there for the asking. The biggest difference with AMD hardware is the onboard memory controller of course. I suspect that Apple/IBM will either have to move to this soon especially if the current FSB starts to have problems scaling. In other words if they have to go to a 3 to 1 bus at 3GHz I think we will start to see pressure for an integrated memory controller. We might also see this presure if they put a G4 derived processor with an integrated memory controller into a portable and it shows considerable improvements.

Ultimately Power5 seems to have solutions to some of the problems discussed. The primary one being the on board memory interface.

Dave
post #69 of 122
<gurgle>

Sorry, I have to drop out of this discussion. NDAs are a bitch.
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post #70 of 122
Wizard, I think that I have been unclear.

What I meant, is that IBM has two lines of processor the power line and the PPC line. Apple will never use the powerline in his desktop computers.

That do not mean, that the PPC line will not benefit from some improvements coming from the power line, like SMT and multicore, nor the powerline will not benefit from improvements coming from the PPC line like altivec.
post #71 of 122
Must be tough to sit there and watch the rest of us project (geuss) where the porcessor line is going!!!

In any event I don't think the wait is all that long. Another round of 970 derived chips and then on to the next generation is my geuss. This new hardware could be avialable soon in the new year.


Actually of late my interest has been directed more at the portable low power market. Some of the noise coming from IBM seems to indicate a huge jump in capability soon with respect to the portable market. That noise however does not specifically say the portable chip is ready but hey we can hope. Hoping is more than I was doing even a couple weeks ago.

Dave


Quote:
Originally posted by Programmer
<gurgle>

Sorry, I have to drop out of this discussion. NDAs are a bitch.
post #72 of 122
Quote:
Originally posted by wizard69
Must be tough to sit there and watch the rest of us project (guess) where the porcessor line is going!!!

You have no idea.
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post #73 of 122
Obviously you can't talk about what you know, but which post here would a wise man ignore?

I'm fairly lucky with what I'm doing now. Totally unrelated to anything discussed here. In fact just the mention of Apple products causes people to ask if they are still in business around here.

Thanks
dave


Quote:
Originally posted by Programmer
You have no idea.
post #74 of 122
Hi Guys;

Came across something interesting while combing through the change log for the latest Linux kernel. I also posted this snip over on Ars.
Quote:
[PATCH] Create cpu_sibling_map for PPC64
\t
\tIn light of some proposed changes in the sched_domains code, I coded up
\tthis little ditty that simply creates and populates a cpu_sibling_map for
\tPPC64 machines. The patch just checks the CPU flags to determine if the
\tCPU supports SMT (aka Hyper-Threading aka Multi-Threading aka ...) and
\tfills in a mask of the siblings for each CPU in the system. This should
\tallow us to build sched_domains for PPC64 with generic code in
\tkernel/sched.c for the SMT systems. SMT is becoming more popular and is
\tturning up in more and more architectures. I don't think it will be too
\tlong until this feature is supported by most arches...

Now that last sentence seems to indicate that SMT is not far off for desktop processors. It is unknown if the individual actually knows what the future is about to deliver or if he is just geussing about future directions.
It does give me a little hope that the future with SMT is not that far away.

Now the question that comes to mind is this a future with Power5 derived hardware or is it a future with SMT bolted onto a 970. One also has to consider is Power5 just Power4 with SMT bolted on. Yeah I know there is more to it than that but I hope everyone gets the general idea. Personally I think the Power5 derived core would be the path of least resistance.

Thanks
Dave
post #75 of 122
Thread Starter 
Quote:
Originally posted by wizard69
Hi Guys;

Came across something interesting while combing through the change log for the latest Linux kernel. I also posted this snip over on Ars.


Now that last sentence seems to indicate that SMT is not far off for desktop processors. It is unknown if the individual actually knows what the future is about to deliver or if he is just geussing about future directions.
It does give me a little hope that the future with SMT is not that far away.

Now the question that comes to mind is this a future with Power5 derived hardware or is it a future with SMT bolted onto a 970. One also has to consider is Power5 just Power4 with SMT bolted on. Yeah I know there is more to it than that but I hope everyone gets the general idea. Personally I think the Power5 derived core would be the path of least resistance.

Thanks
Dave

My take on this is that he is talking about the 970 and the like. It has been my experience that when people are talking about the POWER series that is how they refer to it POWER. When people are referring to the 970 and the like they say PPC the 64 part just nails it as being 970 like, as opposed to other versions of the PPC that are not 64. Yes it does look like SMT is coming soon like maybe in the March revision time frame. We all knew that clock rate increases at least at the 90 level is expensive, in many ways, to do. So the promise to Apple is performance increases, some equate that only with clock rate others know that there are many different technologies that can come to the PPC 9XX processors and give them significant performance increases and never need to increase the clock rate, not saying that IBM cannot increase the clock rate, but I would rather have these technologies rather than have another 500MHz clock raate increase. I tend to think that these other technologies like SMT, more cores, on die memory controller, rapid IO, improved Altivec, and the like add up to more than 500MHZ performance wise.
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post #76 of 122
Quote:
Originally posted by Tomb of the Unknown
You mean, "Neither does the POWER4!"

See any Macs with POWER4's in them? No?

Gee, wonder why?

If you run OSX in one of IBM's POWER4 machines, isn't that a POWER4 Mac? Not that I am doing that, I am just asking.
post #77 of 122
Quote:
Originally posted by Tidris
If you run OSX in one of IBM's POWER4 machines, isn't that a POWER4 Mac? Not that I am doing that, I am just asking.

Short answer: No.

Long answer: Try it some time.
"Spec" is short for "specification" not "speculation".
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post #78 of 122
Quote:
Originally posted by Tomb of the Unknown
Short answer: No.

Long answer: Try it some time.

And why not? If you hide the POWER4 box under a desk, who would know the difference? My point is that what most people call a "Mac" is not the hardware but the user experience one gets from using the OSX software. If you run LINUX on an Apple G5 machine, is that a Mac? I say absolutely not because the user experience is completely different. So, by my way of thinking, a POWER4/POWER5 Mac is very feasible because all it takes is porting OSX to any of the fine IBM POWER5 boxes. All Apple has to do is refrain from suing whoever is doing the porting .
post #79 of 122
Quote:
Originally posted by wizard69
Obviously you can't talk about what you know, but which post here would a wise man ignore?

Nice try.

Quote:
I'm fairly lucky with what I'm doing now. Totally unrelated to anything discussed here. In fact just the mention of Apple products causes people to ask if they are still in business around here.

Normally I post here freely because I don't know anything about Apple's plans either.
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post #80 of 122
Quote:
Originally posted by Programmer
Normally I post here freely because I don't know anything about Apple's plans either.

Niether do I so post away I will!

Lots of news coming out lately. Now IBM has indicated that they are moving Hypervisor support or something similar into one of the next PPC chips. If SMT support is there also then I'd have to say it is pretty clear that the next or 2nd to the next PPC is in fact derived from Power5.

Now the question is how soon can Apple and IBM actually deliver working systems? I'm still thinking that something this big will probally wait for WWDC though a big boost at MWSF would be nice.

Dave
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