Originally posted by Programmer
Why on earth would anyone think that IBM could make a short pipeline design run at 5.6 GHz when their previous short pipeline designs can barely crack 1 GHz and Motorola's only recently reached a paltry 1.67 GHz?
To play Devil's advocate: Why on Earth would anyone think that Freescale would hitch a 4GHz CPU to a 167MHz SDR bus? The relative immobility of MaxBus has stretched the CPU:bus clock ratio about as far as it can reasonably go, and so Freescale has used almost all their improvements in design and process to reduce cost, power consumption, and "hot spots." That's where their progress has been made for the last couple of years.
Until MaxBus is dead, there's no point even contemplating a design like Cell's that requires massive bandwidth.
And, of course, after MaxBus is dead, the G4 core will not magically become optimized for high Hz. But it should be able to scale up more quickly than it has done.
This thing is a long pipeline design, end of story. The whole chip is designed for throughput and pipelining while trying to hide long latencies at every turn, what makes you think that the Power core would be any different?
I agree based on my own intuition, but I'm reading other things from people who know more about these things than I do (at Ars, mostly).
While I have your attention, for my own edification, what is "FO4," and why is IBM so happy to have reduced it?
I used to like David Every's writings, but for the last 6 or so years he really hasn't had much to contribute and tends to have too many errors in his articles (this one in particular has quite a few). Charging for it seems ridiculous.
Agreed. RIP MacKiDo. He wasn't always right then, either, but he was right more often, and certainly more interesting, than he's been for a while now.