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Cell details

post #1 of 135
Thread Starter 
http://home.businesswire.com/portal/...40&newsLang=en

234 million transistors and 221 mm^2 @ 4GHz !

(Edit: I was in such a rush to post this, I forgot to proof-read the title)

[edit by Amorph: Fixed title. ]
post #2 of 135
Thread Starter 
More details:

Quote:
The new processor will include Rambus interfaces called FlexIO Processor Bus and XDR RAM for memory. Together these interfaces provide up to 100 gigabytes per second of aggregate CPU bandwidth, said Rich Warmke, director of marketing for the memory interface division at Rambus.

At 4GHz with eight logical processors, this thing or some derivative is undoubtedly going to be in the next PowerMac. This seems to be a multicore Power5 derivative--or the converse. Since this has been in development since 2001, it could be that the Power 5 SMT features are derived from Cell!
post #3 of 135
In other NEWS Rambus is claiming :
Quote:
The new processor will include Rambus interfaces called FlexIO Processor Bus and XDR RAM for memory._ Together these interfaces provide up to 100 gigabytes per second of aggregate CPU bandwidth, said Rich Warmke, director of marketing for the memory interface division at Rambus.
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post #4 of 135
Quote:
Originally posted by Aphelion
NEWS

"The Cell chip will go into production by midyear at IBM's East Fishkill, N.Y. wafer factory. Sony"

If this time frame is correct then we may be looking at a WWDC June/July introduction of a new PowerMac. We could get speed bumps soon?
post #5 of 135
Thread Starter 
Here's some wikipedia info direct from the conference attendees.

Quote:
While the Cell chip can have a number of different configurations, the workstation and PlayStation 3 version of Cell consists of one "Processing Element" ("PE"), and eight "Attached Processing Units" ("APU"). The PE is based on the POWER Architecture, basis of their existing POWER line and related to the PowerPC used by Apple Computer and others. The PE is not the primary processor for the system, but acts as a contoller for the other eight APUs, which handle most of the computational workload.

Each APU is a VLIW 128-bit vector processor with a 1024-bit external bus. The bus is attached to an 8MB high speed memory, one for each APU, which is also visible to the PE to be loaded with data and programs as needed. The APU's memory is also connected to the next APU in line, allowing data to be processed by one APU and then handed off to the next at very high speed. In general use the system will load the APUs with small programs, known as apulettes, chaining the APUs together to handle each step in a complex operation. For instance, a set top box could load up apulettes for reading a DVD, video and audio decoding, and display, and the data would be passed off from APU to APU until finally ending up on the TV. Each APU is expected to give 32 GFLOPS of performance, thereby giving the entire Processing Unit 256 GFLOPS of performance.

and,

Quote:
Cell allows for multiple processing units to be put onto one die, and the patent (http://patft.uspto.gov/netacgi/nph-P...XT&p=1&p=1&S1=) showed four on one die, called the "Broadband Engine", potentially giving over 1 Teraflops of performance. It is unclear how many processing units will be incorporated into either the PlayStation 3 or workstations.
post #6 of 135
Sorry to kill the ambiance here, but I am not sure at all that the Cell is really a desktop chip.

If you look at his architecture, it's a fantastic multimedia chip, perfect for MP encoding for example, but I doubt it's perfect for let's say bureautic applications or applications who do not use parallelar code.

The cell is perhaps the paradigm of the RISC architecture : simple units (the power PC architecture are not really simple) working in parallelar at very high speed.
But if you put complex code, the emulator would have to break it in many Apulets, and I think that we might see an huge performance penalty : adios the 256 gflop.
Remember that the chip in the PS2 have many gigaflops of power, but it do not say it all.

Cell architecture is may be not for tommorow in macs. The PPC 64 bit line, have a lot of room to increase. A dual core PPC 970, seems more a logical choice for 2006.
post #7 of 135
This Cell chip could mean bad news for Apple hardware sales. Why? Because Sony and Toshiba will be selling Cell-based consumer level hardware that should in theory be able to run OSX and should be very price competitive with anything Apple can offer.
post #8 of 135
I suppose you could have a 'mini grid' of cells for a Desktop machine but I reckon it would be impracticle and expensive over the current technology.
A PS3 will use Cell technology but a PS3 isn't a very flexible machine. This doesn't mean it can't be adapted for the Desktop but I'm sure there will be major coding changes to use the cell effieciently/normally.
I will be a bit more attentive to both MS and Intel reports on future software/hardware paths as they will certainly be able to size up if the cell technology is a threat or not.

Dobby.
post #9 of 135
Quote:
Originally posted by Tidris
This Cell chip could mean bad news for Apple hardware sales. Why? Because Sony and Toshiba will be selling Cell-based consumer level hardware that should in theory be able to run OSX and should be very price competitive with anything Apple can offer.

Glass half empty.

Apple's smaller base and Hardware Abstration for OSX makes it "easier" for them to move to another hardware platform. You guys are missing real point. Intel and AMD are the ones that need to be back pedaling and launching FUD campaigns. If Cell tech provides average general computing and Gonzo multimedia it's still a better option as multimedia is going to be where the future profits are.
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post #10 of 135
sony and Steve J.

"who knows maby someday computers and music too"


cell might just be that music....
post #11 of 135
What does this mean that Cell will be able to run any OS?
post #12 of 135
From http://www.scee.presscentre.com/imag...etailsID=25555
  • SUMMARY:
  • Cell is a breakthrough architectural design -- featuring 8 Synergistic Processing Units (SPU) with Power-based core, with top clock speeds exceeding 4 GHz (as measured during initial laboratory testing).
  • Cell is OS neutral - supporting multiple operating systems simultaneously
  • Cell is a multicore chip comprising 8 SPUs and a 64-bit Power processor core capable of massive floating point processing
  • Special circuit techniques, rules for modularity and reuse, customized clocking structures, and unique power and thermal management concepts were applied to optimize the design

    CELL is a Multi-Core Architecture
  • Contains 8 SPUs each containing a 128 entry 128-bit register file and 256KB Local Store
  • Contains 64-bit Power ArchitectureTM with VMX that is a dual thread SMT design views system memory as a 10-way coherent threaded machine
  • 2.5MB of on Chip memory (512KB L2 and 8 * 256KB)
  • 234 million transistors
  • Prototype die size of 221mm2
  • Fabricated with 90nanometer (nm) SOI process technology
  • Cell is a modular architecture and floating point calculation capabilities can be adjusted by increasing or reducing the number of SPUs

    CELL is a Broadband Architecture
  • Compatible with 64b Power Architecture
  • SPU is a RISC architecture with SIMD organization and Local Store
  • 128+ concurrent transactions to memory per processor
  • High speed internal element interconnect bus performing at 96B/cycle

    CELL is a Real-Time Architecture
  • Resource allocation (for Bandwidth Management)
  • Locking caches (via Replacement Management Tables)
  • Virtualization support with real time response characteristics across multiple operating systems running simultaneously
    CELL is Security Enabled Architecture
  • SPUs dynamically configurable as secure processors for flexible security programming

    CELL is a Confluence of New Technologies
  • Virtualization techniques to support conventional and real time applications
  • Autonomic power management features
  • Resource management for real time human interaction
  • Smart memory flow controllers (DMA) to sustain bandwidth
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post #13 of 135
Quote:
Originally posted by Tidris
This Cell chip could mean bad news for Apple hardware sales. Why? Because Sony and Toshiba will be selling Cell-based consumer level hardware that should in theory be able to run OSX and should be very price competitive with anything Apple can offer.

I have a hard time seeing much bad news for Apple here. Whether or not Apple ends up using the Cell chip itself, the fabrication and research on this chip are going to find there way into the PowerMac sooner or later. This just shows that IBM is a great partner when it comes to hardware--not falling behind like Motorola did.
post #14 of 135
Quote:
Originally posted by Tidris
This Cell chip could mean bad news for Apple hardware sales. Why? Because Sony and Toshiba will be selling Cell-based consumer level hardware that should in theory be able to run OSX and should be very price competitive with anything Apple can offer.

Nonsense.
post #15 of 135
Thread Starter 
Quote:
Originally posted by Ompus
From http://www.scee.presscentre.com/imag...etailsID=25555
  • .
    .
    .
    CELL is a Multi-Core Architecture
  • Contains 8 SPUs each containing a 128 entry 128-bit register file and 256KB Local Store
  • Contains 64-bit Power ArchitectureTM with VMX that is a dual thread SMT design views system memory as a 10-way coherent threaded machine
  • 2.5MB of on Chip memory (512KB L2 and 8 * 256KB)
    .
    .
    .


The Sony playstation is going to having Altivec in it!

VMX = Altivec(TM)

Also, remember that Altivec was one of the things IBM incorporated into the PPC970 at Apple's request, circa 2001. This thing is going to Macs, no doubt about it.
post #16 of 135
Gotta agree, wow I really didn't take the time to notice the VMX.

The barriers towards Mac use are falling one by one.
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post #17 of 135
Superficially, it looks like a Power5 derivative CPU, having 64 bit registers, SMT and VMX. This CPU is surrounded by 8 additional vector SPUs, which might be considered coprocessors?
post #18 of 135
Quote:
Originally posted by Tidris
This Cell chip could mean bad news for Apple hardware sales. Why? Because Sony and Toshiba will be selling Cell-based consumer level hardware that should in theory be able to run OSX and should be very price competitive with anything Apple can offer.

OMG no.

Apple is fine. There is a whole lot more than the CPU in a computer. We don't even know if a CELL can replace any of Apple's CPUs or if it is just a coprocessor based on the PPC instruction set.
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post #19 of 135



It is very possible that OSX can run directly on the Cell chip's PPC core processor. Whether it can address the 8 SPE's ("synergistic processing units") through Tiger's Core services is something only Apple's system engineer's know.

I don't expect to see any Apple product sporting a Cell chip until next year at the earliest, however I do expect the next generation of the 970 to appear in time for a Powermac this Summer followed by a low power version for the Powerbook.

The next PowerPC for Apple will benefit from the Power5 features that are mentioned in the Cell.

This is all good news for Apple.
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post #20 of 135
Cell runs a flavor of Unix and has Altivec.
Cell is going into HD TVs made by Sony.
It's also described as ideal for audio, video and graphics.
The rumored Tiger OS may have support for many parallel processors.
Perhaps someone at Apple has noticed.
post #21 of 135
Quote:
Originally posted by Existence
234 million transistors and 221 mm^2 @ 4GHz !

The editor must have been excited about the 4 GHz too.
So he forgot to mention the speed of the POWER core - 1 GHz. 4 GHz is for the APUs only.

I would prefere a 970MP @ 3 GHz
post #22 of 135
Quote:
Originally posted by smalM
I would prefere a 970MP @ 3 GHz

Especially if it had a Cell co-processor (or co-processors) to handle real time rendering as well as HD encoding & decoding! (Not to mention my broadband connection).
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post #23 of 135
I doubt we'll see an actual Cell processor in a Mac anytime soon (if ever), but I do think we'll be seeing Power, and Cell derived PowerPC processors fairly soon. I posed the question months ago if IBM had been working on cell based processors for a few years now, wouldn't we be seeing benefits of what they have learned from this technology in upcoming Power, and PowerPC processors? I think all the years of testing on multiple cells, and multiple cores alone puts IBM at an advantage when producing a multi-core PPC processors. With all that testing, and prototyping that must have been done I'm sure they have learned a few lessons, and found a few pitfalls that they now know to avoid. I'm sure they have discovered more than that alone, but my point is that they are at a great advantage in dealing with multi-core, technology. If only they would take one lesson from AMD and throw in that on-die memory controller everybody keeps talking about that is so highly regarded as being the key to the overwhelming performance of the Opteron processors.
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post #24 of 135
Quote:
Originally posted by onlooker
I doubt we'll see an actual Cell processor in a Mac anytime soon (if ever), but I do think we'll be seeing Power, and Cell derived PowerPC processors fairly soon.

This really doesn't make sense to me. What does "Cell derived PowerPC" mean? The Cell contains a Power processor, so how would you derive a Power processor from it?

Any why wouldn't we see a Cell processor in a Mac? Assuming Apple can see how nicely their CoreXXXX technologies map onto a bunch of really fast vector processors (duh!), and once this thing gets into production (or a variation that has the balance of components that Apple wants... maybe 2 Power cores and only 4 SPUs, for example).

Cell is really about the System-on-chip and the small specialized cores so that you can afford a lot of them. Careful chip design and you get some pretty impressive clock rates and power consumption numbers.
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post #25 of 135
Concerning Apple and CELL, has anyone bothered to check whether or not GCC has any references for the CELL instruction sets?
post #26 of 135
Quote:
Originally posted by Programmer
This really doesn't make sense to me. What does "Cell derived PowerPC" mean? The Cell contains a Power processor, so how would you derive a Power processor from it?

The meaning is in the rest of the post.
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post #27 of 135
cell is a powerpc. it need a brand new mainboard (that need a new kext) but ic can now run os x from 10.0. to 10.4. but it run like a g3 @ 4GHz. to use the vector unit apple must made the dirt work and make it accessible to developer like an altivec extension (if spu are altivec is esier)
noe look in prospective: insert a multicore power (for application that can' t be parallelized) and more spu (for all core image apps)....
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post #28 of 135
Quote:
Originally posted by Existence
The Sony playstation is going to having Altivec in it!

VMX = Altivec(TM)

Also, remember that Altivec was one of the things IBM incorporated into the PPC970 at Apple's request, circa 2001. This thing is going to Macs, no doubt about it.

I thought the PS2 already had two vector processing units in addition to the core processor within the Emotion Engine?

But anyway, all this tech will never be bad news for Apple. The question is at what point will we see some of this filter into the computers?
post #29 of 135
Quote:
Originally posted by DaveLee
I thought the PS2 already had two vector processing units in addition to the core processor within the Emotion Engine?

But anyway, all this tech will never be bad news for Apple. The question is at what point will we see some of this filter into the computers?

Your correct. LSI's processor design, and vector processing unit is not Altivec, and is probably closer to the design that will be used in the PS3. Motorola has patented their design heavily. If however the Playstation is using the Altivec design this time I'm sure Motorola is getting paid for it. Or will be when they find out.
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post #30 of 135
Quote:
Originally posted by onlooker
Your correct. LSI's processor design, and vector processing unit is not Altivec, and is probably closer to the design that will be used in the PS3. Motorola has patented their design heavily. If however the Playstation is using the Altivec design this time I'm sure Motorola is getting paid for it. Or will be when they find out.

I know that when the PS2 was launched, and for some time after the games programmers made little use of the vector units (the novelty?) in a similar way to the issuse which faced Apple and coding for the Altivec unit on the G4.

With that in mind, and if the VMX unit in Cell is similar enough to Altivec, what are the specific implications for a general code base which use these units (in games and in future software)? Does code require specificity for it's use or can it be 'ported' around for various different software applications?
post #31 of 135
I seem to remember reading an online article showing IBM's recent patents and one of those related to a compiler that could optimize code for, I think it mentioned, multiple processes or threads or something. I'll look again, but this could be interesting times ahead.
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post #32 of 135
So Programmer, what do you think the odds are for Apple to drop Altivec support from the G6 and to simply forward such calls to a dedicated Cell CPU? This would reduce the G6 complexity and cost. You could treat Cell like an old math coprocessor.

This way the Power5 to G6 transition is simpler (no bolting on Altivec).

This way it is easier to cram multiple cores into a single G6 die because you have reduced the complexity of each core.

This way you don't have oddly redundant Altivec units on both the main CPU and the Cell CPU.

This way you could probably squeeze some extre MHz out of the G6 because you don't have to time your communication with the Altivec registers/etc.

Thoughts? I'm not up to date wrt the latest G6 rumors, all I know is that is is two cores on the die.
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post #33 of 135
Quote:
Originally posted by Yevgeny
So Programmer, what do you think the odds are for Apple to drop Altivec support from the G6 and to simply forward such calls to a dedicated Cell CPU? This would reduce the G6 complexity and cost. You could treat Cell like an old math coprocessor.

Zero.

What is the one word that processor designers never mention when introducing their latest and greatest chips?

Latency



Quote:
This way the Power5 to G6 transition is simpler (no bolting on Altivec).

Given that they have at least 2 VMX implementations now, I don't see how that is a real problem. Especially with IBM's automated design tools.

Quote:
This way it is easier to cram multiple cores into a single G6 die because you have reduced the complexity of each core.

Why have multiple G6 cores when you can have even more SPUs? Most problems that can be made parallel also benefit from using vector units.

Quote:
This way you don't have oddly redundant Altivec units on both the main CPU and the Cell CPU.

People keeping saying "why have both" or "these are redundant"... but they are not. There is good reason to have both and they fulfill different purposes.

Quote:
This way you could probably squeeze some extre MHz out of the G6 because you don't have to time your communication with the Altivec registers/etc.

No more so than with the GPR/FPR files. The VMX unit doesn't slow down the chip -- you just have to look at all 9 cores on the Cell to see that!

Quote:
Thoughts? I'm not up to date wrt the latest G6 rumors, all I know is that is is two cores on the die. [/B]

There are no G6 rumors. There are dual core G5 rumors. If I had to start one I'd say G6 == Cell.


BTW: IBM was an equal partner in the initial VMX development so I'm quite sure that they do not pay Motorola/Freescale (or Apple for that matter) a cent.
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post #34 of 135
Quote:
Originally posted by Programmer
Zero.

Thanks for the answers.
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post #35 of 135
Altivec uses ~10-12 million transistors, depending on implementation. It's not a millstone around the PowerPC's neck, and it becomes a less significant addition with every processor generation. By contrast, the execution logic of a Cell SPE takes up 7 million transistors.

It can also do tricks that no other SIMD unit (that I've heard of, and including the SPE's in Cell) can do.

And finally, it was designed to be integrated into the core of a PowerPC. It needs the low latency because the work it's used for frequently involves use of the scalar units as well (e.g., computing array indexes and pointer offsets). Isolating AltiVec as a separate core makes no sense. This is why the SPE's are a new design rather than being derived from AltiVec.
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post #36 of 135
Quote:
Originally posted by Programmer


. . . BTW: IBM was an equal partner in the initial VMX development so I'm quite sure that they do not pay Motorola/Freescale (or Apple for that matter) a cent.


I believe it depends on the agreement, or contract, these three companies made. If all three had equal share in development of the vector unit, it could be wise to share equally in license fees. This way, if Sony and Toshiba produce these chip, IBM, Freescale and Apple will be paid equally for its use. For that matter, both IBM and Freescale may have been paying fees all along. Then again, the three inventors may have free use of the patent for products they manufacture. This would leave Apple out in the cold financially, however.

BTW, I think you are right about the cell being the G6 or whatever Apple wants to call it. The cell chip changes everything. For example, the G4 might have been Apple's low end CPU, and the G5 used in higher performance Macs. Now, I believe the Cell will be in everything. The low end Macs will have a lower performance version. It's just a question of when the transition takes place. I think Tiger may already have capability of using the SPEs, or SPUs, for the core services. If not, Apple is working on it now.
post #37 of 135
A couple articles mention that the PE, or central CPU, in the Cell has a VMX unit. It's already there if these authors are correct.

http://en.wikipedia.org/wiki/Cell_chip

This article was already referenced near the beginning of the thread.
post #38 of 135
Thread Starter 
Excellent website full of Cell details:

http://www.blachford.info/computer/Cells/Cell6.html



Quote:
APU = SPE or SPU.
PU = PPE.

* Clock speed over 4GHz.
* 100 GBytes per second aggregate Memory & I/O speed:
* - Dual XDR controller gives 25.6 GBytes per second.
* - Dual configurable interfaces give 76.8 GBytes per second.
* 8 X "SPEs", 128 bit vector engines, 128 registers each.
* 2 instructions issued per cycle per SPE.
* Peak = 256 GigaFlops
* Double precision maths operations supported.
* 256KBytes "Local Store" per SPE.
* Internal communication is via 4 X 128 bit rings, up to 96 Bytes per cycle.
* PPE can handle 2 threads, this pretty much means it's taken from the POWER5.
* PPE includes VMX.
* PPE includes 512 KBytes Cache.
* "Dynamic Power Management" technology.
* Ten heat sensors
* 221 square mm in 90nm.
* 234 million transistors
* 90nm SOI, Low K, 8 layers of metal & Copper interconnect.
* IBM start manufacturing within 6 months, Sony to start later in the year.

Multiple simultaneous operating systems including Linux.

Apple may be involved as VMX (aka AltiVec) was an Apple initiative, with this the PPE core should boot OS X with little modification.

Looks like some architectural changes have been made since the patent application:

* Local Memory sizes have increased, they are now 256KBytes.
* Local memory is also referred to as "locking cache" so it may have the functionality of a cache as well a "local memory". The patent explicitly stated it was not a cache.
* The internal 1024 bit bus was not implemented, there is an internal bus system which runs at up to 96 bytes per clock.
* SPEs appear to contain an MMU and a DMA controller. Patent application did not mention a MMU in the SPEs.

I predict new PowerMacs within 8 months using Cell or a Cell variant.
post #39 of 135
Imagine when these things start showing up as standard across the entire Mac line-up...!

A Mac mini with a "smaller" Cell...?!?

Forget about it!

PC users will not be able to stop from switching, intel will crumble, M$ will flounder...

Sweet!
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post #40 of 135
Looks like IBM is finally going to use a low-k dielectric for the 90 nm fab. Combined with dual-liner strained silicon, a svelt Powerbook G5 will be very possible.

For Cell, it's not exactly a panacea. Depending on what the PPE architecture is like, it could be a worse performer at scalar ops than the G4 is. Also, 221 sq mm die running in excess of 2 GHz. It must be a concidence than no power numbers are bandied about for the entire chip.

100+ Watts for a 3 GHz chip? Can't wait to see the box that Sony will ship the thing in.
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