One thing I haven't seen mentioned yet: there have been rumours of MPX-based DDR motherboards around for over a year now. That implies that Apple has had a working chipset for at least that long, and hasn't released it yet. It may be that they didn't want to get hammered for using a "hack solution" in their desktop/notebook machines. The benchmarked performance improvement just wouldn't be enough to warrant it, but it actually made a lot of sense for a server. Only after a great deal of testing would they feel comfortable releasing a server based on a "new" chipset (at least I hope that is the case!). This means that they had the chipset design lying around anyhow, so why not use it for something even though a completely new chipset & processor was just about to arrive.
This implies, of course, that they are waiting for a bigger leap. As I said above, the on-chip memory controller / RapidIO bus design should be cheaper to build than the MPX-based design due to RIO being a fast & narrow bus and the memory being kept close ot the processor. It makes a lot of sense for all of Apple's other machines: towers, iMac, iBook, PB. Cheaper, better, faster.
There is another alternative as well, that I'll throw into the ring while I'm at it, just to muddy the waters further: Apple has been designing their own chipsets for years, and that level of integration gives them lots of advantages. They can (and have) built a chipset that talks to all the devices in the system, which means that the processor only needs to talk to the chipset. Currently no other devices talk to the processor via MPX. This means to replace the MPX all you need to do is replace the processor and the chipset. Chipset is obviously a no-brainer, and we all have heard that Apple has gotten more involved in the processor design end of things. So while Motorola prefers RapidIO for a lot of good reasons (from their point of view), Apple doesn't really care about it that much... and they sit on the HyperTransport consortium. Imagine, if you will, a 12 gigabyte/second pipe from the CPU to the memory controller which is completely under Apple's control. This situation would be one of great happiness and joy for Apple because now they could design a killer motherboard to feed their processor's voracious appetite. Put multiple HyperTransport links onto the chipset along with bus snooping logic and you have a muliprocessor. If you get buddy buddy with ATI and/or nVidia and they give you a HyperTransport graphics solution (they are on the HT consortium as well, and talking it up -- sockets have to be coming soon) then you've got massive bandwidth to the graphics engine as well. You also avoid the problems inherent in a per-processor memory design.
No evidence, of course, but it does show that there are other possibilities.
Providing grist for the rumour mill since 2001.
Providing grist for the rumour mill since 2001.
