Originally posted by melgross
Really? Show us otherwise. I'm merely going by what Hannibal said in Ars. If you don't believe him...
If you say "Well, we know that the PU is based on the G4, and the SPU on the 601" to Mr Stokes, he'll be laughing his derriere off. He didn't say such a thing.
And yes he knows about CPU design, but it's like what happens in journalism. One is only as good as the information available, and sometimes there just isn't any good information received, and journalists must be creative. Mr Stokes' speculative article about Apple jumping to Intel for cheap ARM processors for iPods is a pretty good demonstration of that.
from Hannibal: "The actual architecture of the Cell SPE is a dual-issue, statically scheduled SIMD processor with a large local storage (LS) area. In this respect, the individual SPUs are like very simple, PowerPC 601-era processors." ... "It's (PPC core) also in-order issue, like the SPUs."
Note the keywords, "are like" and "PowerPC 601-era processors." He's making an analogy that the SPEs are similar to in-order narrow-issue processors in the mid-90s. That's all, just an analogy.
The Cell SPE is not "based" on the 601. By "based" I mean IBM took the design of the 601 and modified it. That's where the laughable part comes in. If anything the Cell SPE seems to be based on a modified VMX unit with a CPU front end (fetch, dispatch et al) and a small amount of local memory attached.
For the Cell PPE and its cousin the Xenon PPE, as far as we know, it is based on an IBM high clock rate research processor called Ravina 4 to 5 years ago. It was not based on any G4 processor of any kind.
from Hannibal: "Sure, it'll pack a major SIMD punch, but that will not be a double-precision Alitvec-type punch."
Strange thing to say since AltiVec doesn't do double-precision ops of any kind.