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IBM ready to deliver dual-core PowerPC G5 processors? - Page 3

post #81 of 97
Quote:
You might be surprised at the relative power of the PU vs. an SPU.

Care to elaborate? Don't be shy...

Lemon Bon Bon
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post #82 of 97
Quote:
Originally posted by Lemon Bon Bon
Care to elaborate? Don't be shy...

Lemon Bon Bon

He's not shy!
post #83 of 97
Quote:
Originally posted by melgross
Well, we know that the PU is based on the G4, and the SPU on the 601.



Yeah, right.
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post #84 of 97
Quote:
Originally posted by Programmer


Yeah, right.

Really? Show us otherwise. I'm merely going by what Hannibal said in Ars. If you don't believe him...

This is some of it. If I have time later I'll look some more.

"As you can see, IBM has eliminated the instruction window and its attendant control logic, in favor of adding more storage space and more execution hardware. A Cell SPE doesn't do register renaming or instruction reording, so it needs neither a rename register file or a reorder buffer. The actual architecture of the Cell SPE is a dual-issue, statically scheduled SIMD processor with a large local storage (LS) area. In this respect, the individual SPUs are like very simple, PowerPC 601-era processors."

"It's (PPC core) also in-order issue, like the SPUs."

"Finally, before signing off, I should clarify my earlier remarks to the effect that I don't think that Apple will use this CPU. I originally based this assessment on the fact that I knew that the SPUs would not use VMX/Altivec. However, the PPC core does have a VMX unit. Nonetheless, I expect this VMX to be very simple, and roughly comparable to the Altivec unit o the first G4. Everything on this processor is stripped down to the bare minimum, so don't expect a ton of VMX performance out of it, and definitely not anything comparable to the G5. Furthermore, any Altivec code written for the new G4 or G5 would have to be completely reoptimized due to inorder nature of the PPC core's issue.

So the short answer is, Apple's use of this chip is within the realm of concievability, but it's extremely unlikely in the short- and medium-term. Apple is just too heavily invested in Altivec, and this processor is going to be a relative weakling in that department. Sure, it'll pack a major SIMD punch, but that will not be a double-precision Alitvec-type punch."
post #85 of 97
Off topic, but I couldn't help myself

Quote:
Originally posted by melgross
....<snip>...what Hannibal said in Ars. If you don't believe him...<snip>...

So the short answer is, Apple's use of this chip is within the realm of concievability, but it's extremely unlikely in the short- and medium-term. Apple is just too heavily invested in Altivec, and this processor is going to be a relative weakling in that department. ...<snip>...

Apparently, Apple suprised everyone, me included, too heavily invested in Altivec, riiiight. Apple's version of shock and awe.
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post #86 of 97
Quote:
Originally posted by rickag
Off topic, but I couldn't help myself




Apparently, Apple suprised everyone, me included, too heavily invested in Altivec, riiiight. Apple's version of shock and awe.

You have helped yourself.

You're missing the point of the dissussion. It's not that Apple went to the x86 and changed their plans, it's the comparison between the Cell and the G4 and G5 that we're talking about. Your comment is out of context.
post #87 of 97
Ok, I found some more of Hannibal's stuff here.

"The Xenon PPE details given above have since been officially confirmed, which makes it extremely likely that, with the very important exception of the Xenon's VMX hardware, the Cell's PPE shares its architecture with the three cores that make up the CPU that powers the Xbox 360. This being the case, the present discussion will rely heavily on what is known of the Cell's PPE to describe the Xenon's cores.

Before moving on, though, I should take a brief moment to quash a rumor that I unfortunately had a significant hand in starting last year. I originally thought that the PPE design shared by the Cell and the Xenon was derived from the PowerPC 970/POWER5 lineage. This is certainly not the case for a number of reasons, not the least of which is the fact that if IBM could produce a triple-core 970 derivative we'd certainly have seen at least a dual-core 970 derivative in a Mac by now. Some, lacking clear IBM documentation on the matter, are inclined to persist in the belief that the Xenon's PPE may be a 970 derivative, but as far as I'm concerned the case is settled."

Edit:
Article published June 01, 2005
post #88 of 97
Quote:
Originally posted by melgross
You're missing the point of the dissussion. It's not that Apple went to the x86 and changed their plans, it's the comparison between the Cell and the G4 and G5 that we're talking about. Your comment is out of context.

I know.

I didn't miss the point.

Didn't you see my statement at the very begining of the post that said,"Off topic, but I couldn't help myself". Of course what I said was "out of context", it was Off Topic.

Relax, it was supposed to be somewhat funny.
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post #89 of 97
Quote:
Originally posted by rickag
I know.

I didn't miss the point.

Didn't you see my statement at the very begining of the post that said,"Off topic, but I couldn't help myself". Of course what I said was "out of context", it was Off Topic.

Relax, it was supposed to be somewhat funny.

Yes, I know it was.
post #90 of 97
Quote:
Originally posted by melgross
Really? Show us otherwise. I'm merely going by what Hannibal said in Ars. If you don't believe him...

If you say "Well, we know that the PU is based on the G4, and the SPU on the 601" to Mr Stokes, he'll be laughing his derriere off. He didn't say such a thing.

And yes he knows about CPU design, but it's like what happens in journalism. One is only as good as the information available, and sometimes there just isn't any good information received, and journalists must be creative. Mr Stokes' speculative article about Apple jumping to Intel for cheap ARM processors for iPods is a pretty good demonstration of that.

Quote:
from Hannibal: "The actual architecture of the Cell SPE is a dual-issue, statically scheduled SIMD processor with a large local storage (LS) area. In this respect, the individual SPUs are like very simple, PowerPC 601-era processors." ... "It's (PPC core) also in-order issue, like the SPUs."

Note the keywords, "are like" and "PowerPC 601-era processors." He's making an analogy that the SPEs are similar to in-order narrow-issue processors in the mid-90s. That's all, just an analogy.

The Cell SPE is not "based" on the 601. By "based" I mean IBM took the design of the 601 and modified it. That's where the laughable part comes in. If anything the Cell SPE seems to be based on a modified VMX unit with a CPU front end (fetch, dispatch et al) and a small amount of local memory attached.

For the Cell PPE and its cousin the Xenon PPE, as far as we know, it is based on an IBM high clock rate research processor called Ravina 4 to 5 years ago. It was not based on any G4 processor of any kind.

Quote:
from Hannibal: "Sure, it'll pack a major SIMD punch, but that will not be a double-precision Alitvec-type punch."

Strange thing to say since AltiVec doesn't do double-precision ops of any kind.
post #91 of 97
Quote:
Originally posted by THT
If you say "Well, we know that the PU is based on the G4, and the SPU on the 601" to Mr Stokes, he'll be laughing his derriere off. He didn't say such a thing.

And yes he knows about CPU design, but it's like what happens in journalism. One is only as good as the information available, and sometimes there just isn't any good information received, and journalists must be creative. Mr Stokes' speculative article about Apple jumping to Intel for cheap ARM processors for iPods is a pretty good demonstration of that.



Note the keywords, "are like" and "PowerPC 601-era processors." He's making an analogy that the SPEs are similar to in-order narrow-issue processors in the mid-90s. That's all, just an analogy.

The Cell SPE is not "based" on the 601. By "based" I mean IBM took the design of the 601 and modified it. That's where the laughable part comes in. If anything the Cell SPE seems to be based on a modified VMX unit with a CPU front end (fetch, dispatch et al) and a small amount of local memory attached.

For the Cell PPE and its cousin the Xenon PPE, as far as we know, it is based on an IBM high clock rate research processor called Ravina 4 to 5 years ago. It was not based on any G4 processor of any kind.



Strange thing to say since AltiVec doesn't do double-precision ops of any kind.

Yes, they are similar to that old design. Are they actually based on the lithography? Probably not. The point is that they are similar to an old simple design that hasn't used for many years. The same concept. That's what I mean by "based".

Sure, as far as YOU know. But the G4 has been mentioned before in this context by other writers in this area.

None of it has been based on the G5 which is what Programmer thinks.

his speculations were before the Cell came out and there was little information available. There is now.

And after all, your speculation is just that.
post #92 of 97
Quote:
Originally posted by melgross
Yes, they are similar to that old design. Are they actually based on the lithography? Probably not. The point is that they are similar to an old simple design that hasn't used for many years. The same concept. That's what I mean by "based".

I'm fine with similar or analogous. And similar only in the sense of in-order, narrow-issue. That's really as far as it goes. They are not similar in design much at all. I don't think anyone would call a 21 stage pipeline, single ALU, FPU and SIMD unit CPU with 2-way SMT based on G4 processor.

Quote:
Sure, as far as YOU know. But the G4 has been mentioned before in this context by other writers in this area.

Only in the context of in-order, narrow-issue. As far as design, they are not similar whatsoever.

Quote:
None of it has been based on the G5 which is what Programmer thinks.

I've had long discussions with Programmer before, and in those discussions, he never intimated Cell was based on the 970 architecture at all.
post #93 of 97
Quote:
Originally posted by THT
. . . I've had long discussions with Programmer before, and in those discussions, he never intimated Cell was based on the 970 architecture at all.

I'll agree with this; it is my impression too. He explicitly mentioned the in-order nature of the Cell PPE and what effects this would have on performance, depending on how the code is written.
post #94 of 97
Quote:
Originally posted by THT
I'm fine with similar or analogous. And similar only in the sense of in-order, narrow-issue. That's really as far as it goes. They are not similar in design much at all. I don't think anyone would call a 21 stage pipeline, single ALU, FPU and SIMD unit CPU with 2-way SMT based on G4 processor.



Only in the context of in-order, narrow-issue. As far as design, they are not similar whatsoever.



I've had long discussions with Programmer before, and in those discussions, he never intimated Cell was based on the 970 architecture at all.

That was the feeling I got from his posts.

I have also read in several articles that the PPE was derived (again those words) from the G4. I'l try to find those as well, but they're several months old now, so we'll see.
post #95 of 97
The PPE (and the rest of the Cell) was designed from scratch. You can find a feature in every processor that is similar to some feature in some previous processor, but so what?

Really the only way to know the performance of the PPE is to run code on it.
post #96 of 97
Gee, the PPU has registers too, does that mean it was based on some other older processor with registers?

Minor superficial similarities in processor architectures do not imply any real architectural relationship. Further, the other gents are correct: the Cell's PPU and SPUs have no architectural relationship to the G3, G4, G5 or POWER4-5, and I have never implied or stated that they do. The PPU design is most likely an outgrowth of a IBM high clock (well, for the time anyhow: 1GHz) research project, and is probably the same basic core as used in the XBox360 (although MS has clearly modified their verison to get VMX128 and 3 cores).


As for future hardware directions... I think I'll just let you find out the hard way.
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post #97 of 97
Quote:
Originally posted by Programmer
Gee, the PPU has registers too, does that mean it was based on some other older processor with registers?

Minor superficial similarities in processor architectures do not imply any real architectural relationship. Further, the other gents are correct: the Cell's PPU and SPUs have no architectural relationship to the G3, G4, G5 or POWER4-5, and I have never implied or stated that they do. The PPU design is most likely an outgrowth of a IBM high clock (well, for the time anyhow: 1GHz) research project, and is probably the same basic core as used in the XBox360 (although MS has clearly modified their verison to get VMX128 and 3 cores).


As for future hardware directions... I think I'll just let you find out the hard way.

Yes, it's well known now that it is the same basic core as the Xenon.
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