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Intel to ship quad-core server chip in early 2007

post #1 of 16
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Intel expects to ship its first processor with four cores in early 2007, a high-ranking company executive said on Friday.

The new chip, code-named Clovertown, will include four processing cores to process data more quickly and run multiple application processes simultaneously, all while using less power than a single-core design, Intel CTO Justin Rattner told reporters on Friday.

The new chip will join Intel's line of server chips, dubbed Xeon, which have proven to be a lucrative business for the world's largest chip maker, generating billions in revenue. However, the business has recently come under pressure from Sunnyvale, Calif.-based AMD, which has entered the server market with its own line of chips called Opteron.

In proving the Clovertown chipset is well along in its development cycle, Rattner demonstrated a working server with a pair of the new microprocessors, but declined to say whether all four cores are on a single die, or if Clovertown would use two dual-core chips stuck together.

"We are well along in the validation process of this new design," he said in an interview on the company's Web site. "It has been showing such robust performance we decided that it was time to let people see it."

Rattner said Intel will release the chips, which will be manufacturered on a 65-nanometer processes, in early 2007 -- possibly starting revenue shipments as early as late 2006.

Rattner also predicted that within the next ten years, a single chip will have tens or even hundreds of cores. "It's kind of like how many angels can you fit on the head of a pin?" he said. Still, the exec acknowledged that there are significant challenges in breaking beyond eight or 16 cores milestone, such as how to provide enough system memory or teach developers to take advantage of the new features in their software applications.

News of Clovertown may be of interest to Apple followers, as there has been very little (if any) news on the company's plans for its Xserve enterprise servers moving to the Intel platform.

The last significant update to Xserve line came over a year ago, in January of 2005, when Apple updated the servers to dual 2.3GHz PowerPC G5 processors.
post #2 of 16
Quote:
Originally posted by AppleInsider
In proving the Clovertown chipset is well along in its development cycle, Rattner demonstrated a working server with a pair of the new microprocessors, but declined to say whether all four cores are on a single die, or if Clovertown would use two dual-core chips stuck together.

I think the odds are pretty good (90%?) that Cloverton is a dual-chip MCM. Ie, 2 CPUs in one package like most of the P4 "dual-cores" are. And presumbly, the MCM will have the same 1333 MHz FSB. (There would be 2 FSBs with Intel's DIB architecture, so one FSB per 4 cores with Cloverton).

Not quite sure where all these cores are leading us though, especially for consumers. The MHz has to continue to go up, or rather, the single threaded performance has to go up to effectively increase the performance of apps across the board. If it is just increasing cores, it's going to be a long slow slog to get performance increases in a lot of apps; however, many of those apps are [not] CPU-constrained. Still...

[edit: grr...]
post #3 of 16
When will Intel add on an integrated memory controller like AMD has on some of its processors? From what I read about this chip, all four cores will be sharing one path to memory.

I checked Intel's roadmap and couldn't find squat about an onboard (integrated) memory controller...
post #4 of 16
One thing is clear for the future: native and savvy multicore-multiprocessor-multithreaded applications (including the operating system itself) will be a must in the future. This also opens the possibility to run multiple operating systems on the same machine.
post #5 of 16
Quote:
Originally posted by sc_markt
When will Intel add on an integrated memory controller like AMD has on some of its processors? From what I read about this chip, all four cores will be sharing one path to memory.

I checked Intel's roadmap and couldn't find squat about an onboard (integrated) memory controller...


Hmmmmm I think this proc may support Intel's forthcoming Dual Independant Bus (DIB). I can't see them getting good performance on a Quad Core without DIB.
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post #6 of 16
Quote:
Originally posted by hmurchison
Hmmmmm I think this proc may support Intel's forthcoming Dual Independant Bus (DIB). I can't see them getting good performance on a Quad Core without DIB.

From arstechnia:

"As I pointed out in a post on Intel's major 2006-2007 weak spot, these four-core processors will be crammed into a socket that's fed by an out-of-date front-side bus. This bandwidth problem will be exacerbated by the fact that Intel still won't have an on-die memory controller, which means that memory traffic will be flowing to all four cores over that single, dated FSB. "

This sort of sounds like the G4: A decent chip hobbled with a slow bus.

You would think that a large and major semiconductor company such as Intel would have the intellectual abilty to design a memory controller on their microprocessors by now...

link
post #7 of 16
Quote:
Originally posted by hmurchison
Hmmmmm I think this proc may support Intel's forthcoming Dual Independant Bus (DIB).

DIB means independent bus per CPU not per core.
Tigerton (4 cores on 1 die) is expected to have a new independant bus for each core.
Cloverton (2x Woodcrest MCM) will have one FSB. But 10.6 GB bandwidth isn't too shabby 8)
post #8 of 16
Quote:
Originally posted by sc_markt
From arstechnia:

"As I pointed out in a post on Intel's major 2006-2007 weak spot, these four-core processors will be crammed into a socket that's fed by an out-of-date front-side bus. This bandwidth problem will be exacerbated by the fact that Intel still won't have an on-die memory controller, which means that memory traffic will be flowing to all four cores over that single, dated FSB. "

This sort of sounds like the G4: A decent chip hobbled with a slow bus.

You would think that a large and major semiconductor company such as Intel would have the intellectual abilty to design a memory controller on their microprocessors by now...

link

Please...Ars is a terrible place for articles. All their writers are biased little pricks with no insight of the the future.
post #9 of 16
Quote:
Originally posted by smalM
DIB means independent bus per CPU not per core.
Tigerton (4 cores on 1 die) is expected to have a new independant bus for each core.
Cloverton (2x Woodcrest MCM) will have one FSB. But 10.6 GB bandwidth isn't too shabby 8)

What does DIB mean this time around? With the Pentium Pro and successors, the second bus was a cache bus, I can't tell if it is still the same here.
post #10 of 16
Quote:
Originally posted by JeffDM
What does DIB mean this time around? With the Pentium Pro and successors, the second bus was a cache bus, I can't tell if it is still the same here.

DIB = dual independent [front-side] bus. Here's an illustration with Cloverton (or Kentsfield) as a 2 CPU MCM equating to 4 cores per package or module, and the so-called Allendale as a 2 MB L2 "Woodcrest/Conroe/Merom". Who knows with Intel's code names. It's even worse that particle physics. It's pretty much like the Power Mac G5 2 socket systems.

Code:


better

Cloverton or Kentsfield Cloverton or Kentsfield
--------------------------------- ---------------------------------
| | | |
| ------------------------- | | ------------------------- |
| | | | | | | | | |
| | Core | Core | | | | Core | Core | |
| | 1 | 2 | | | | 1 | 2 | |
| | | | | | | | | |
| |-------------------------| | | |-------------------------| |
| | 2 MB L2 | | | | 2 MB L2 | |
| | (Allendale) | | | | (Allendale) | |
| ------------------------- | | ------------------------- |
| | | | | | | | | | | |
| ------------------------- | | ------------------------- |
| | | | | | | | | |
| | Core | Core | | | | Core | Core | |
| | 1 | 2 | | | | 1 | 2 | |
| | | | | | | | | |
| |-------------------------| | | |-------------------------| |
| | 2 MB L2 | | | | 2 MB L2 | |
| | (Allendale) | | | | (Allendale) | |
| ------------------------- | | ------------------------- |
| | | | | | | | | | | |
--------------------------------- ---------------------------------
| | | | | | | |
| | | | DIB | | | |
| | | | <---- Dual Independent Bus ----> | | | |
| | | | | | | |
| | | ------------- ------------- | | |
| | ------------- | | ------------- | |
| ------------- | | | | ------------- |
------------- | | | | | | -------------
| | | | | | | |
1067/1333 MHz FSB 1 | | | | | | | | 1067/1333 MHz FSB 2
with 1 socket | | | | | | | | with 1 socket
| | | | | | | |
----------------------------------
| ------------------------------ |
| | | |======= DDR2-667 Channel 1
| | | |
| | | |======= DDR2-667 Channel 2
| | Northbridge | |
| | | |
| | | |======= PCIe
| | | |
| | | |======= Southbridge
| ------------------------------ |
----------------------------------



Bad:

Cloverton or Kentsfield
---------------------------------
| |
| ------------------------- |
| | | | |
| | Core | Core | |
| | 1 | 2 | |
| | | | |
| |-------------------------| |
| | 2 MB L2 | |
| | (Allendale) | |
| ------------------------- |
| | | | | |
| ------------------------- |
| | | | |
| | Core | Core | |
| | 1 | 2 | |
| | | | |
| |-------------------------| |
| | 2 MB L2 | |
| | (Allendale) | |
| ------------------------- |
| | | | | |
---------------------------------
| | | |
| | | |
---------------------------------
| |
| ------------------------- |
| | | | |
| | Core | Core | |
| | 1 | 2 | |
| | | | |
| |-------------------------| |
| | 2 MB L2 | |
| | (Allendale) | |
| ------------------------- |
| | | | | |
| ------------------------- |
| | | | |
| | Core | Core | |
| | 1 | 2 | |
| | | | |
| |-------------------------| |
| | 2 MB L2 | |
| | (Allendale) | |
| ------------------------- |
| | | | | |
---------------------------------
| | | |
| | | |
| | | | 1 1067/1333 MHz FSB with 2 sockets
| | | |
| | | |
----------------------------------
| ------------------------------ |
| | | |======= DDR2-667 Channel 1
| | | |
| | | |======= DDR2-667 Channel 2
| | Northbridge | |
| | | |
| | | |======= PCIe
| | | |
| | | |======= Southbridge
| ------------------------------ |
----------------------------------

post #11 of 16
Quote:
Originally posted by sc_markt
From arstechnia:

"As I pointed out in a post on Intel's major 2006-2007 weak spot, these four-core processors will be crammed into a socket that's fed by an out-of-date front-side bus. This bandwidth problem will be exacerbated by the fact that Intel still won't have an on-die memory controller, which means that memory traffic will be flowing to all four cores over that single, dated FSB. "

This sort of sounds like the G4: A decent chip hobbled with a slow bus.

You would think that a large and major semiconductor company such as Intel would have the intellectual abilty to design a memory controller on their microprocessors by now...

link

It's not a big deal for 1 or 2 socket systems, which is the vast majority of systems sold.

It's not like a G4 either since the G4 FSB is 2 to 4 times slower than contemporary memory performance, while Intel's FSB matches contemporary memory standards. With Intel being the volume king, it is probably that way for that reason, unless a company wants to be a rebel and use XDR-DRAM or something.

The current memory standard is dual channel DDR-400 to dual channel DDR2-533 which equates to 6.4 to 8,5 GB/s bandwidth.

G4 FSB at 167 MHz = 1333 MB/s which is 4x to 6x slower.

Intel FSB at 1067 MHz = 8.5 GB/s bandwidth, which so happens to match dual channel DDR2-533.

When DDR2-667 is volume and prevalent, Intel will bump their FSB to 1333 MHz bandwidth. When DDR2-800 is volume and prevalent, Intel will bump their FSB to 1600 MHz bandwidth.

Heck, it won't be until this Summer that AMD will move to DDR2-533/667/800. They are still at DDR-400/466/533 I think.

The primary point about the arstechnica article is in 4+ socket systems where inter-socket communication becomes a critical factor. AMD's Hypertransport can directly link the sockets to each other instead of communicating through a FSB or other means, at least for 4 sockets.

But in a 1 or 2 socket system, Intel will have about the same memory performance as a quad-core "Athlon" system. This is all assuming AMD will stick with dual channel memory controllers, which is a pretty good assumption. So, not really a big deal.
post #12 of 16
ok, so by mwsf '07 the lineup should look like this:

macbook/macbook pro : merom ?

imac : merom or conroe ?

promac (?) : woodcrest ( quads ) ?

o almost forgot

mini : merom celeron?

what do you guys think?
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post #13 of 16
Quote:
Originally posted by smalM
DIB means independent bus per CPU not per core.

I'm guessing you mean per chip - not per CPU? "Each Core is" literally "a CPU".

I would hope by the time intel makes this processor they have something better figured out.
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post #14 of 16
Quote:
Originally posted by onlooker
I'm guessing you mean per chip - not per CPU? "Each Core is" literally "a CPU".

A CPU is a CPU is a CPU

For me CPU = central processing unit = 1 chip. Was a long time true since the times of CPU + MMU + FPU = 3 chips. But I might have to reconfigure my vocabulary...
post #15 of 16
There is some more info regarding the Conroe chip om the DailyTech website. It is reporting that the next genration chip will gain SSE4 and bring some "Significant Video Enhancements". I wonder if this will help accelerate H624 and add some Altivec like features.

http://www.dailytech.com/article.aspx?newsid=788
post #16 of 16
Quote:
Originally posted by onlooker
I'm guessing you mean per chip - not per CPU? "Each Core is" literally "a CPU".

Not really. A core is a core and a processor is a chip, at least so say the manufacturers of the things. Software writers are the only people that disagree and that's only because there is profit in it for them, and even then most take the side of the hardware manufacturers.
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