Originally Posted by Mr. H
I'm sorry I'm not being precise enough in my wording, and maybe I'm wrong about Tiger (I didn't realise that it didn't do any x86-64, I'd assumed its 64-bit status on Intel was the same as that on PPC).
Wow, I'll have to retract my statement.
Apple must have quietly added x86-64 support in a later build of 10.4.7, because mine of 10.4.8 does have a x86-64 version of libSystem.
That's odd, though, because I've never heard anyone reporting that.
Yeah, Tiger only supports ppc32, ppc64 and x86-32 (IA32).
This would explain why the 10.4.8 update included a rather sizable upgrade of the BSD subsystem, although I have yet to find any binary that actually takes advantage of this, and in addition, there is no way in Xcode 2.x (3.0 doesn't run on Tiger because it uses Objective-C 2.0) to actually compile for 64-bit. (I have not checked whether the 10.4.8-shipped gcc itself allows such compilations, which could then manually be merged using lipo.)
Certainly, though, lipo has been updated to recognize this new binary segment type, because I'm positive I checked this just a while ago (10.4.6? 10.4.7?), and it didn't work.
Sorry for my above mistake.
When I talk about Napa/Santa Rosa, I assume that you know what I mean. I'm well aware that Napa/Santa Rosa are the codenames for the whole Centrino platform, not the actual northbridge/southbridge chipsets, but it is much more convenient to use the Napa and Santa Rosa codenames because the chipset codenames are not well known.
Yes, I know what you mean and I often use those names myself for simplicity. That said, I still haven't seen any evidence that the chipset would impose such a limit. A 4 GB limit, perhaps (effectively causing the 3.x GB limit). Or, more likely, lack of PAE. Since most of OS X runs in 32-bit mode regardless (and this won't change until Leopard), PAE would still be needed, as I understand it, for the bulk of apps.
This is incorrect! It would seem that there is an OS and chipset issue. The OS can't address more than 4 GB, and Intel themselves have confirmed that the chipset can't address more than 3.2 GB (or whatever it was) of RAM.
But have Intel confirmed the reason for that limitation? Is it truly with the chipset, or inherent in architectural problems?
Hopefully we can agree it's got nothing to do with the Core 2 Duo (Merom),
what with the way that that's an x86-64 chip and therefore capable of performing the necessary memory addressing calculations.