A Parting Question...
...as I head to the cabinet for some Nyquil and then bed, I leave you guys with this question, now that we know what the speed bump / new processor is (and isn't).
Given how long it [has taken Apple to redesign the PM architecture in the past], how likely are the following specs to be included in the next major PowerMac rev? I say given where we are, and that none of these technologies would be expensive for Apple to use, the chances are pretty good.
G4's running between 1 and 1.4 GHz
266 MHz system bus (UMA 3 anyone?)
PC2100 RAM (cheaper than I thought)
800 Mbps Firewire
Two (or three) spare USB ports, NOT including the one the keyboard is plugged into
Continued rebates / low prices on 17" LCD screen
[ 01-29-2002: Message edited by: Moogs ? ]</p>
Given how long it [has taken Apple to redesign the PM architecture in the past], how likely are the following specs to be included in the next major PowerMac rev? I say given where we are, and that none of these technologies would be expensive for Apple to use, the chances are pretty good.
G4's running between 1 and 1.4 GHz
266 MHz system bus (UMA 3 anyone?)
PC2100 RAM (cheaper than I thought)
800 Mbps Firewire
Two (or three) spare USB ports, NOT including the one the keyboard is plugged into
Continued rebates / low prices on 17" LCD screen
[ 01-29-2002: Message edited by: Moogs ? ]</p>
Comments
400-500 MHz bus.
ddr RAM
If no G5 until MWSF, then new PMG4s at MWNY:
"Apollo" G4 (essentially the current G4 fabbed on a 0.13 µm process)
1.0, 1.133, 1.266 MHz (1.0, 1.1, 1.3 GHz), duals on either the 1.1, or 1.3 GHZ)
266 MHz bus
DDR RAM
Based only on rumor, it seems that the G5 is going to clock from 1.2-1.8 GHz. If so, then it would seem that Apple will want to squeeze in another G4 update to bridge the gap between the current top speed of 1 GHz, and the PMG5 low end of 1.2 GHz. It would be unprecedented for Apple to render the dual 1 GHz powermac obsolete in the next powermac update, by setting the low end powermac at 1.2 GHz. Unfortunately, it's not good business sense (although I think these are extenuating circumstances, because Apple is playing catch-up in the public perception).
What really pains me is that the current Powermacs are actually very impressive computers. With that fast 2 MB L3 cache it will be interesting to see some real-world benchmarks (done by an independent party, not by Apple). The mid and high end Powermacs could probably almost keep up with a 2 GHz pentium, but the low end probably blows, since Apple neutered it (no L3 cache). What I mean is that there is a performance gap, but it's so small that it shouldn't be the basis of choosing between a Mac or Wintel (except for gamers). But the press and most consumers really think that Powermacs are half as fast as Wintels! I blame the media for this because of the way they constantly jabber and gush about the latest clock speeds of Intel chips. Most of these journalists know less about computers than the average ChumpUSA salesman, and yet they "educate" the public about computers!
Wouldn't it be great if computers were compared by something other than MHz? Why can't speed be rated by instructions per second, "flops", as Apple does? I would really like to see a comparison of the G4 with Pentium 4 and Athlon, using gigaflops. Apple should do this and plaster it all over the airwaves during primetime TV. WTF doesn't Apple do this?
[quote]The problem with a faster bus (and faster memory) is that the processor has to support it, and there is no sign of such a processor. If the just-introduced 7455 is the Apollo then we can't expect DDR support until the G5.<hr></blockquote>
Why can't the Apollo support a new, faster system bus and by extension DDR RAM? Is it not technically possible for Apple to simply design a new mobo for existing and future Apollo chips to run on? Where's the technical barrier...this doesn't make any sense to me (though I'm not an engineer obviously).
I mean, if they were going to up the speed of the bus *at all* they would be likely to do a complete revision, right? Doesn't make sense financially do simply (redesign the bus to)bump the speed another 33 MHz or something like that - DOES IT??
If we really have to wait for a new chip architecture before we can use a new bus architecture, that is not good news IMO. [edit]
[ 01-29-2002: Message edited by: Moogs ? ]</p>
The G5 will come with a new motherboard and all the other stuff we want (DDR, ATA 100 etc) and form the real Pro line up.
Why waste time and energy redesigning the G4 tower when the future is gonna be G5?
This is the last speedbump before the G5 is launched, I reckon.
<strong>Quote from Programmer:
Why can't the Apollo support a new, faster system bus and by extension DDR RAM? Is it not technically possible for Apple to simply design a new mobo for existing and future Apollo chips to run on? Where's the technical barrier...this doesn't make any sense to me (though I'm not an engineer obviously).
I mean, if they were going to up the speed of the bus *at all* they would be likely to do a complete revision, right? Doesn't make sense financially do simply bump the bus speed another 33 MHz or something like that - DOES IT??
If we really have to wait for a new chip architecture before we can use a new bus architecture, that is not good news IMO. [edit]
As for your last sentence about Apollo, it seems to contradict the first sentiment you put forth. Can Apple design a new, more modern mobo for Apollo to run on or not, and if so, why wouldn't they do so right away (if they haven't started already)?
[ 01-29-2002: Message edited by: Moogs ? ]</strong><hr></blockquote>
I think you missed the point of my message... if the 7455 chip just released is what we've been calling Apollo (i.e. 7451+SOI), then we won't get DDR until the G5 because there has been no word about further G4 developments. If, however, this is not the Apollo and that will come out as the 7460, presumably process shrunk, then one of the things they could change in the design is increasing the bus speed. This is quite a significant change to the chip, however, as designing a fast motherboard bus is no small matter -- it is much harder to double the clock rate of a bus that stretches inches instead of millimeters, and has traces you can see with the naked eye.
I don't know which we'll get. There are strong arguments that the G5 won't arrive until 2003, and there is a lot of rumour and wishful thinking that it'll arrive in the next 6 months. The worst situation would be if the G5 arrives in 2003 and there are no further G4 chips aside from a straight process shrink... and that is the rumour in another thread.
Sorry about the last paragraph of my response to you - I figured out what you meant by "if it is Apollo" after I posted, and then edited my post.
At any rate, would it not make sense that the next process change - since we've now gone to SOI - is to shrink the 7455 down to .13 µ (thus resulting in the 7460), right? I mean that's more probable than an entirely new chip like the G5, no? Especially if the G5 is meant to be done on the same process (.13µÂ*SOI).
Either way though, why would it be hard for Apple to design a new mobo/system bus that pushes up to the 266MHz level? Surely others have done it already, otherwise there would be no reason for RAM manufacturers to make PC2100 DIMMs, much less try and sell them. I fail to see where the hang-up is.
I understand it's harder to squeeze faster clock rates out of a system bus because of the distances involved, but it seems this magnitude of barrier has already been overcome by other players in the PC world - and it was done some time ago, not just recently. True?
On a tangent, would it be easier or harder for Apple to design a faster bus / implement DDR RAM with the existing 7455, or with the 7460 as described above?
[ 01-29-2002: Message edited by: Moogs Â? ]</p>
Supporting DDR seems to mean either superceding or reengineering MaxBus, unfortunately.
Busses, like processors, can be clocked within a range. MaxBus seems to be able to do 66MHz-133MHz. Changing the bus speed is a simple matter that requires little in the way of engineering (mostly just testing to make sure that the new speed is stable).
We can use the lesson Motorola learned with the 7400 to help figure out what will happen next. The lesson is: Never try a new design on a new process. This tells me that we will not go from a .18 7455 to a .13 85xx. Instead, Motorola will move the 7455 to .13 (mature design on new process), and then fab the G5 once that's up and running well (new design on mature process). It looks like introducing SOI is significant enough to qualify as a "new process," so they might go .18 -> .18+SOI -> .13 -> .13 + SOI, but that's pure speculation on my part.
Of course, if philbot is right and Motorola isn't manufacturing this part, then my heuristic doesn't apply (well, it does, but it has to be reapplied to IBM's product line - they probably won't try a new design on a new process either).
[ 01-29-2002: Message edited by: Amorph ]</p>
So what now? Can Apple possibly design their own FSB to replace the Maxbus currently being used and farm out the fabrication to IBM or some other foundry? If they could, how long would this take from design to being ready to integrate them onto the UMA? Would seem like a relatively easy thing to design and build when compared to say, a new CPU.
<strong>Either way though, why would it be hard for Apple to design a new mobo/system bus that pushes up to the 266MHz level? Surely others have done it already, otherwise there would be no reason for RAM manufacturers to make PC2100 DIMMs, much less try and sell them. I fail to see where the hang-up is.
</strong><hr></blockquote>
Well first of all Motorola would have to extend the G4's bus to double its speed, which requires a fair bit of redesign. Then Apple would need to design a new memory controller to support the new bus.
Its not easy, but sure they could do it... but they've already done it all and its called either RapidIO or HyperTransport, depending on which way they've decided go. And its in the G5. So why go through the effort of designing all that if you're just going to throw it away in the next generation? I suppose its possible that they've done a G4 design with a new bus, but I doubt it since the G5 has been underway so long now -- the effort to update the G4 again would be better spent bringing the G5 to fruition.
I thought it was Motorola's job to design the memory controller and Apple's to integrate it into the mobo?
In essence it sounds like the odds of Apple introducing the next rev of G4's with a faster bus or DDR RAM (even the slower of the two DIMM types) is highly unlikely...although I suppose there's nothing ot stop them from adding an extra Firewire or USB port on the back of the box.
<img src="graemlins/hmmm.gif" border="0" alt="[Hmmm]" />
[ 01-29-2002: Message edited by: Moogs ? ]</p>
Just like with the OS, Macs derive their speed through elegance, GUI and the human interface, not the silicon interface.
I know competitive economics with AMD probably destroyed that notion, but I thought the manufacturing process and relative small size of the chip on the die was still better than Intel.
That would have, should have made MP's as cheap as Pentiums. And if Moto can sell lots of them in embedded devices, can the volume get to that level? Does anyone know how much these Apollo's cost?
<a href="http://www.motorola.com/mediacenter/news/detail/0,1958,1035_747_23,00.html"; target="_blank">www.motorola.com/mediacenter/news/detail/0,1958,1035_747_23,00.html</a>
[ 01-30-2002: Message edited by: CodeWarrior ]</p>
My gut feeling is that if there are significant difficulties in getting the 74xx chips to run with DDR RAM, most effort will being going into G5/DDR developement. I don't think we'll see DDR G4s.
Don't quote me on that though, I'm sure the Moto skunk works has the G4/DDR combo ready to roll out at MWNY or Seybold if Apple is breathing down their necks. <img src="graemlins/lol.gif" border="0" alt="[Laughing]" />
Actually, what am I saying? That'll be the lineup for the Powermacs at MWSF 2003 ... DDR Apollos on .13 SOI, and ATA/133. I lay down a $ on that one
<strong>This Maxbus technology is what is used as the front side bus on Apple's motherboards, right?</strong><hr></blockquote>
Yes, and lack of DDR support aside, it's quite nice. THT has opined in another thread that by now it can probably be clocked as high as 200MHz (the Mot FAQ, where the 133MHz limit is given, is several fab generations old at this point, and smaller generally implies faster). At 200MHz, it could take advantage of DDR SDRAM.
Apple's own memory controller would have to be revamped to handle that as well.
[quote]<strong>So what now? Can Apple possibly design their own FSB to replace the Maxbus currently being used and farm out the fabrication to IBM or some other foundry?</strong><hr></blockquote>
That would require redesigning the CPU itself. For all we know, Motorola is doing that right now. Or not.
If the rumors are right, the G5 class processors will have the memory controller on board (and since this particular rumor is based on the fact that the specs for the only known G5 class processor - the 8540 - list an onboard memory controller, this is a safe bet), and that will remove one bottleneck and save Apple some trouble and silicon as well. That architecture should support DDR at the very least.
Apple, for its part, would have to redesign the Memory Bus portion - which provides a bridge from the memory bank to the memory controller. It must also redesign said memory controller - all in order to make the use of DDR DIMMS possible given the correct processor combinations.
SO, the question then becomes, given that it is not technically difficult (from what I can tell) to do this, what is the impetus for spending the R&D (especially for MOT who is struggling mightily)? Obviously, we can make the argument that even if the G4 lasts another solid year in terms of being reved, this is not enough to warrant them redesigning the MPX bus. But, if the new iMac and the latops *also* use the MPX bus or similar variant, wouldn't *that* be reason enough to design one and get it into Macs ASAP?
Especially given that the 7455 processor we're seeing now (or a process shrink of same, call it 7460) will likely be used in all Apple portables and iMacs for at least the next 18-24 months?
In short, isn't it unreasonable to assume that the *only* use for a redesigned MPX bus (and Apple Memory Bus / Controller) is the PowerMac line? Sure, Motorola may want to focus more on the G5's onboard controller, but meantime won't it still need to improve MPX and get it integrated with new controllers from Apple so that the other product lines can benefit from faster DDR?