Hypertransport, Rapid-I/O, DDR-SDRAM comments.
AN interesting comment that I found at <a href="http://www.cubezone.com"; target="_blank">www.cubezone.com</a> (below)
In response to someone asking about HyperTransport in the new macs.
It is highly unlikely that Hypertransport is in the new PowerMac's. They simply put all those system features into one chip. That is right at the edge of what you can do in one chip. And many server PC's do have GE on the system controller, some have more than one PCI. The purpose of HT is to allow multiple chips to connect together with few pins, and with only one chip this is not needed. Apple is at the edge of capability and needs to go further as does the rest of the industry. A single 33Mhz PCI is simply not adequate for server type applications, even if it is 64 bit. You are likely to see HT in an upcoming G5, where I expect the memory controller will be on the CPU! Processors need to get Main Memory closer to them, so they will be including a Memory controller right on chip very soon. Some embedded processors have already done this, and the stand alone processors are not far behind. So you will see a main processor with a fast DDR-SDRAM port for main memory, perhaps a tertiary cache bus (like currently) (DDR or QDR SRAM), and one, two, or three Hypertransport busses for all I/O. If there is only one HT bus, then a HT switch chip will be connected to it providing several HT links. One will likely go to the graphics subsystem, one to a PCI interface chip, and one to an I/O chip with GE, Firewire, USB, and ATA ports. The whole architecture looks a lot different. No AGP port, perhaps more than one PCI bus to support 66MHZ (which apple cannot do with its central system controller right now), Disk (and GE and Firewire), will connect to a HT link, not PCI. No time for a picture, sorry. The hitch in all this is that Motorola is supporting RapidIO which is an alternative bus to HT. It will be interesting to see what the G5 has!!! I bet it is HT.
P.S. There is NO WAY that the G4 used DDR SDRAM for its cache. It is DDR SRAM, a very different chip. Someone needs to tell apple, it looks really bad that they don't know what they are talking about.
SO is this guy right about the DDR SRAM cache memory?
MSKR
In response to someone asking about HyperTransport in the new macs.
It is highly unlikely that Hypertransport is in the new PowerMac's. They simply put all those system features into one chip. That is right at the edge of what you can do in one chip. And many server PC's do have GE on the system controller, some have more than one PCI. The purpose of HT is to allow multiple chips to connect together with few pins, and with only one chip this is not needed. Apple is at the edge of capability and needs to go further as does the rest of the industry. A single 33Mhz PCI is simply not adequate for server type applications, even if it is 64 bit. You are likely to see HT in an upcoming G5, where I expect the memory controller will be on the CPU! Processors need to get Main Memory closer to them, so they will be including a Memory controller right on chip very soon. Some embedded processors have already done this, and the stand alone processors are not far behind. So you will see a main processor with a fast DDR-SDRAM port for main memory, perhaps a tertiary cache bus (like currently) (DDR or QDR SRAM), and one, two, or three Hypertransport busses for all I/O. If there is only one HT bus, then a HT switch chip will be connected to it providing several HT links. One will likely go to the graphics subsystem, one to a PCI interface chip, and one to an I/O chip with GE, Firewire, USB, and ATA ports. The whole architecture looks a lot different. No AGP port, perhaps more than one PCI bus to support 66MHZ (which apple cannot do with its central system controller right now), Disk (and GE and Firewire), will connect to a HT link, not PCI. No time for a picture, sorry. The hitch in all this is that Motorola is supporting RapidIO which is an alternative bus to HT. It will be interesting to see what the G5 has!!! I bet it is HT.
P.S. There is NO WAY that the G4 used DDR SDRAM for its cache. It is DDR SRAM, a very different chip. Someone needs to tell apple, it looks really bad that they don't know what they are talking about.
SO is this guy right about the DDR SRAM cache memory?
MSKR
Comments
And I've been telling you guys Motorola needs to put the memory controller on the processor die forever!
[QB]AN interesting comment that I found at <a href="http://www.cubezone.com"; target="_blank">www.cubezone.com</a> (below)
In response to someone asking about HyperTransport in the new macs.
You are likely to see HT in an upcoming G5, where I expect the memory controller will be on the CPU! Processors need to get Main Memory closer to them, so they will be including a Memory controller right on chip very soon. Some embedded processors have already done this, and the stand alone processors are not far behind. So you will see a main processor with a fast DDR-SDRAM port for main memory, perhaps a tertiary cache bus (like currently) (DDR or QDR SRAM), and one, two, or three Hypertransport busses for all I/O.
G5 will implement RapidIo interconnect bus not HT.
If there is only one HT bus, then a HT switch chip will be connected to it providing several HT links. One will likely go to the graphics subsystem, one to a PCI interface chip, and one to an I/O chip with GE, Firewire, USB, and ATA ports. The whole architecture looks a lot different. No AGP port, perhaps more than one PCI bus to support 66MHZ (which apple cannot do with its central system controller right now), Disk (and GE and Firewire), will connect to a HT link, not PCI. No time for a picture, sorry. The hitch in all this is that Motorola is supporting RapidIO which is an alternative bus to HT. It will be interesting to see what the G5 has!!! I bet it is HT.
HT is a daisy-chain topology and does not define a switch - at least in the first white paper definition, although the switch could be implemented. In contrast to RapidIo the HT does not allowe communication between slave devices in an dasy - chain.
G5 will not incorporate HT.
Rooster