DDR Motherboard

digitalmonkeyboydigitalmonkeyboy
Posted:
in Future Apple Hardware edited January 2014
I remember a while back that there was a lot of talk about "DDR-133" and "DDR-266" being planned for UMA2.



What happened? Will we see DDR 266 on the G5-based motherboard?



Any news of raising the bus speeds?

<a href="http://www.architosh.com"; target="_blank">www.architosh.com</a> claims 400 MHz as a possibility.



[ 12-05-2001: Message edited by: DigitalMonkeyBoy ]</p>

Comments

  • Reply 1 of 10
    outsideroutsider Posts: 6,008member
    I don't think Apple has any choice. They need to beef up their bus and memory throughput. The new G3 (750FX) will support a 200MHz SDR bus, maybe the 7460 will support it too, but doublepumped to 400MHz. That would provide a good basis for the bus speed. Also if there is a G4 it will support RapidIO and that's very fast; about 400-1GHz in the specs on motorolas website. Granted it's a serial 16bit bus (SDR i.e. not double or quad pumped), but that's the way the industry is moving.
  • Reply 2 of 10
    sc_marktsc_markt Posts: 1,402member
    I'm sure DDR will be in the next rev powemac. The reason say this is because right after the summer Macworldexpo '01, I went to the the online Apple store and checked out the new powermac's.

    After you configured one to your preference and clicked "continue" a couple of times, the page that shows you how many you had on order had reference to DDR. For example, if you had 128 Meg ram in your system, the page said SDRAM 128 and at the bottom of the same column, it said DDR. This typo was there for about a month and then it was corrected.



    - Mark
  • Reply 3 of 10
    discstickersdiscstickers Posts: 314member
    Hopefully... Apple desparately needs increased memory bandwidth. Maya would fly on a G5 w/ DDR.
  • Reply 4 of 10
    emaneman Posts: 7,204member
    [quote]Originally posted by sc_markt:

    <strong>I'm sure DDR will be in the next rev powemac. The reason say this is because right after the summer Macworldexpo '01, I went to the the online Apple store and checked out the new powermac's.

    After you configured one to your preference and clicked "continue" a couple of times, the page that shows you how many you had on order had reference to DDR. For example, if you had 128 Meg ram in your system, the page said SDRAM 128 and at the bottom of the same column, it said DDR. This typo was there for about a month and then it was corrected.



    - Mark</strong><hr></blockquote>



    That's weird, I never saw that. Oh well, I guess I just missed it.
  • Reply 5 of 10
    macaddictmacaddict Posts: 1,055member
    lol, I don't think a typo from half a year ago means anything.
  • Reply 6 of 10
    razzfazzrazzfazz Posts: 728member
    [quote]Originally posted by Outsider:

    <strong>Granted it's a serial 16bit bus (SDR i.e. not double or quad pumped), but that's the way the industry is moving.</strong><hr></blockquote>



    Actually, SDR/DDR (single / double data rate) has nothing to do with being a serial / parallel bus, but with how many bits are transmitted per clock cycle per wire.



    Also, "serial 16bit" doesn't make a lot of sense - "serial bus" means "1 bit wide" per definition (I think RapidIO uses multiple [16 probably] serial lines).



    Bye,

    RazzFazz
  • Reply 7 of 10
    kd5mdkkd5mdk Posts: 81member
    How about this question: Will the iMac use DDR? Here's the way I see it:



    Pro:

    Slight economies of scale/implification w/PowerMac

    Will increase iMac performance, and make it a better gaming system.

    Prevents a new MB from being needed in the near future



    Cons:

    Slightly more expensive

    Would reduce differentiation across product lines.



    What do y'all think?
  • Reply 8 of 10
    cyberskiercyberskier Posts: 7member
    [quote]Originally posted by KD5MDK:

    <strong>What do y'all think?</strong><hr></blockquote>



    I think it's ridiculous that Apple hasn't released DDR in their computers yet.
  • Reply 9 of 10
    razzfazzrazzfazz Posts: 728member
    [quote]Originally posted by Cyberskier:

    <strong>I think it's ridiculous that Apple hasn't released DDR in their computers yet.</strong><hr></blockquote>



    It is not. With the current G4 processors (with their front side bus, to be exact), the extra bandwidth offered by DDR RAM would have been completely wasted.



    Bye,

    RazzFazz
  • Reply 10 of 10
    mmicistmmicist Posts: 214member
    [quote]Originally posted by DigitalMonkeyBoy:

    <strong>I remember a while back that there was a lot of talk about "DDR-133" and "DDR-266" being planned for UMA2.



    What happened? Will we see DDR 266 on the G5-based motherboard?



    Any news of raising the bus speeds?

    <a href="http://www.architosh.com"; target="_blank">www.architosh.com</a> claims 400 MHz as a possibility.



    </strong><hr></blockquote>



    Whilst a 400 MHz traditional front side bus is possible, there is nothing in Motorola´s docs that show they have one. Using a 400 MHz bus with 266 MHz RAM doesn´t make all that much sense. However I see two possibilities, RapidIO or Hypertransport, Motorola have RapidIO for their comms chips, but Apple are members of the Hypertransport consortium. My reasoning is:



    The valid information we have from Motorola show an upcoming embedded G5 class chip with an embedded DDR memory controller, the G5 will have an enormous number of pins (about 550 IIRC) and a ridiculous number of logic transistors, which all leads me to believe the G5 will have a separate memory bus and "front side bus". The memory bus will probably a single channel (64 bit) DDR 266 or possibly DDR 333, a dual channel system would be possible but might result in an expensive motherboard and the necessity to add memory DIMMS in matched pairs although a dual channel DDR 333 system would yield 5.4GB/s bandwidth putting even the Pentium4 in the shade. Given a separate memory bus, the front side bus will probably be a hypertransport (400MHz double pumped 16 bit = 1.6GB/s or 32 bit = 3.2GB/s but that would require almost 200 pins by itself) bus, communicating with an AGP bridge and a more-or-less conventional south bridge.



    The problem with a RapidIO bus as a front side bus is that a single pumped 16 bit 400MHz bus would only have 0.8GB/s bandwidth, the same as PC100 memory, which would be just enough to power a 4xAGP and an ordinary PCI bus, but would kill any multiprocessor hopes.



    Michael
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