powerbook cache

in Genius Bar edited January 2014
hi all,

can someone explain me what cache is/does. What's level 1-2-3 cache.

I was wondering since apple is making some fuzz about the 1Mb of cache in the new powerbook. But my good old Lombard also has 1Mb of cache and that's a three year old computer. What's so fantastic about that?




  • Reply 1 of 3
    powerdocpowerdoc Posts: 8,123member
    Memory performance are based upon two factors: the bandwitch and the latency.

    The closer to the CPU , the cache is , the better latency he have.

    The L1 cache has the better latency but is limited in size : 32 Kb for input 32 KB for output, the Athlon have twice this size and the P4 is different in the way that the cache does not contain X86 instructions but microops ones (the P4 is basicaly a risc chip who translate X86 code in more simple code : the microops). So the L1 cache is the fastest of all, but he is limited in size.

    The L2 cache is more bigger and exist in three forms :

    - the first one was on the mobo, like the firsts powermac 9600, the problem is that the memory bandwithc was not impressive, the speed of the cache was the speed of the mobo : 50 mhz for the 9600

    - the second one was directly linked to the chip but outside him: like the pentium 2 and the first generation G3, the pentium 2 was linked via 64 bit at half the clock speed of the pentium. The G3 was able to have different ratio and even a ratio 1/1 but this kind of memory was too expansive and Apple only propose (with some exceptions) memory with a ration 1/2 with amount of cache varying from 256 KB to 1 MByte.

    - the third one was directly built on the chip, On die cache. For example the G3 750 fxe, have a 256 KB L2 cache 64bit wide at full speed, and the sahara is 512 KB L2 cache 256 bit wide (4 time tha bandwitch of the fxe). This kind of L2 cache is the more efficient.

    The L3 cache is the speciality of the 7450 and 7455 chip, it's like an old second type of L2 cache (like the pentium 2), the 7455 support 2 Mb of DDR ram at quarter speed.

    Be carefull Apple is talking of half clock speed but it's because they consider the DDR memory to act at double speed. For the dual ghz the bandwitch is 4 gbyte/sec = 250 * 2 * 8 (64 bit divided by 8 = 8 Byte)

    When a chip need a data, he will start to check the L1 memory, then if he do not found the data the L2 memory then the L3 and at least the main memory.

    [ 05-23-2002: Message edited by: powerdoc ]</p>
  • Reply 2 of 3
    powerdocpowerdoc Posts: 8,123member
    So the difference between your lombard and the new TI book is :

    - the lombard has one MB L2 cache at half clock speed 64 bit wide

    - the new tibook 800 have 256 Kbyte L2 cache 256 bit wide full speed, and 1 MB L3 cache at a quarter the clock speed DDR memory : this L3 cache is as fast at same mhz than the L2 cache of your lombard. Aka 3,2 GB/ second for the 800 mhz.

    [ 05-23-2002: Message edited by: powerdoc ]</p>
  • Reply 3 of 3
    b.b. Posts: 11member
    thank you

    crystal clear now

    nice to see people take an effort to teach the children of a lesser god.

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