Bootable Firewire
Hi. I'm probably going to get an external firewire hard drive soon, and I know it can boot OS 10.2, but does that mean it will for sure be able to boot OS 9.2.2 and Mandrake Linux? The controller chip is the Genesys Logic 700 (I know that the Oxford 911 is the best but an enclosure with that controller costs over twice as much). I've got the specs for it if that would tell anything about it:
GL700Â*Â*Â*Â*IEEE 1394 to ATA/ATAPI Controller
Â*Â*Â*Â*Â* Features
Â? Data transfer rates of S100, S200 and S400
Â? Fully interoperable with implementation of IEEE-1394(1995) and IEEE 1394.a-
Â*Â*Â* Â*Â*Â*Â*Â* 2000Â*compliant
Â? Standard PHY/link Interface
Â? Firmware support for SBP-2 target agent
Â? Semi-automatic SBP-2 protocol management by an internal hardware engine
to improveÂ*performance and firmware efficiency
Â? Auto acknowledge-code response for all packets that targeted to Management
/CommandÂ*ORB agent
Â? SBP-2 protocol engine
-Semi-automatic Management ORB fetch
-Linked Command ORB fetch
-Auto address increment DMA for both direct and indirect addressing
Â? Automatic Page Table fetch
Â? Dedicated asynchronous data transfer
Â? Automatic packing/de-packing for asynchronous transmit/receive data of DMA
Â? Semi-automatic single-retry protocol and split transaction control
Â? Fully ATA-4 compliant
Â? 2 sets of 4-quadlet registers for Asynchronous Receive/Transmit packet header
Â? 2 sets of 8-quadlet registers for general Asynchronous Receive/Transmit packet data block payload
Â? 5 sets of 8/8/2/2/2-quadlet registers for Receive packet data block payload
Â*Â* Â*Â*Â*Â*Â*Â* dedicated forÂ*SBP- requirement (MORB, CORB, PTE, MOP and COP)
Â? 4K bytes of FIFO for bi-directional transmit/receive data
GL700Â*Â*Â*Â*IEEE 1394 to ATA/ATAPI Controller
Â*Â*Â*Â*Â* Features
Â? Data transfer rates of S100, S200 and S400
Â? Fully interoperable with implementation of IEEE-1394(1995) and IEEE 1394.a-
Â*Â*Â* Â*Â*Â*Â*Â* 2000Â*compliant
Â? Standard PHY/link Interface
Â? Firmware support for SBP-2 target agent
Â? Semi-automatic SBP-2 protocol management by an internal hardware engine
to improveÂ*performance and firmware efficiency
Â? Auto acknowledge-code response for all packets that targeted to Management
/CommandÂ*ORB agent
Â? SBP-2 protocol engine
-Semi-automatic Management ORB fetch
-Linked Command ORB fetch
-Auto address increment DMA for both direct and indirect addressing
Â? Automatic Page Table fetch
Â? Dedicated asynchronous data transfer
Â? Automatic packing/de-packing for asynchronous transmit/receive data of DMA
Â? Semi-automatic single-retry protocol and split transaction control
Â? Fully ATA-4 compliant
Â? 2 sets of 4-quadlet registers for Asynchronous Receive/Transmit packet header
Â? 2 sets of 8-quadlet registers for general Asynchronous Receive/Transmit packet data block payload
Â? 5 sets of 8/8/2/2/2-quadlet registers for Receive packet data block payload
Â*Â* Â*Â*Â*Â*Â*Â* dedicated forÂ*SBP- requirement (MORB, CORB, PTE, MOP and COP)
Â? 4K bytes of FIFO for bi-directional transmit/receive data
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