Hmm... that wacky IBM....
Ok, so I'm chillin on ars-technica. And I see this post about a new style of embedded DRAM from IBM <a href="http://www.eet.com/semi/news/OEG20020610S0047"; target="_blank"> EE Times article</a>
Now.. this comment from ars-technica caught my eye.
[quote]It's a clever trick, and it could allow MPU designers who opt to use this instead of SRAM to pack significantly more cache onto the die.<hr></blockquote>
They go on to point out that DRAM requires only 1 transistor per cell, while SRAM requires 4 to 6. Combine this with a .13 micron process... yes, I'm rambling at this point.
Basically I took that, and matched it up with one of the threads in here where JD and Moki were sparring back and forth, with the possible insinuation being thrown out there that IBM may be back in the game. I mean... the big thing goin in computer design right now is bandwidth, right? What's faster than on-die cache?
So here it is, my "out-there" MWNY prediction. A PowerPC chip, supplied by IBM, taking pointers from the POWER4, and leveraging this new tech to offer a big 'ol cache, which is far more feasible if the transistor count required by the cache is reduced by a factor of 4-6. Sounds like something that could feed Altivec nicely.
[ 06-11-2002: Message edited by: ThatGuy ]</p>
Now.. this comment from ars-technica caught my eye.
[quote]It's a clever trick, and it could allow MPU designers who opt to use this instead of SRAM to pack significantly more cache onto the die.<hr></blockquote>
They go on to point out that DRAM requires only 1 transistor per cell, while SRAM requires 4 to 6. Combine this with a .13 micron process... yes, I'm rambling at this point.
Basically I took that, and matched it up with one of the threads in here where JD and Moki were sparring back and forth, with the possible insinuation being thrown out there that IBM may be back in the game. I mean... the big thing goin in computer design right now is bandwidth, right? What's faster than on-die cache?
So here it is, my "out-there" MWNY prediction. A PowerPC chip, supplied by IBM, taking pointers from the POWER4, and leveraging this new tech to offer a big 'ol cache, which is far more feasible if the transistor count required by the cache is reduced by a factor of 4-6. Sounds like something that could feed Altivec nicely.
[ 06-11-2002: Message edited by: ThatGuy ]</p>
Comments
So we either get some juicy G4 with the above or similar clocking at 1.4+
Or Apple is Apple and will release Xserve towers at 1.13ghz and wait until MWSF for the juice.
A month left right?
Why are they needed in memory?
I thought transistors were used in logic.
Why are they needed in memory?
<hr></blockquote>
Transistors are used in digital logic, but digital logic is not the only thing that uses transistors. OP-AMPs, motor controllers, etc all use transistors.
A bit of SRAM can be looked at as some gates in a positive feedback loop. DRAM uses capacitors to store the value of a given bit, but transistors are used to mediate access to a given piece of memory.
A search on Google revealed <a href="http://graphics.stanford.edu/courses/cs448a-01-fall/lectures/dram/."; target="_blank">http://graphics.stanford.edu/courses/cs448a-01-fall/lectures/dram/.</a>; Have a look at slide 19. The left schematic (SRAM) looks like the usual two inverters in a loop with transistors for accessing the value (6 transistors). The right schematic (DRAM) has a capacitor for storing the bit, a transistor for accessing the value (1 transistor).
Edited: It was slide 19, not slide 26. I can't read.
[ 06-12-2002: Message edited by: PipelineStall ]</p>