New G4 with larger L3 cache ?

Posted:
in Future Apple Hardware edited January 2014
If the next version of the G4 lack of DDR memory controller (in that case a larger L3 cache does not matter), don't you think they can get a larger L3 cache to improve the performance ?.



The L3 cache is clocked at quarter speed (if we speak of real clock speed, and not the equivalent in clock speed like do Apple). A 1,2 ghz G4 will have a 300 mhz DDR L3 cache 128 bit wide. This kind of memory still exist in high end graphic card. 32 MB L3 cache already exist in the power 4.



Don't you think that a 32 MB L3 cache (costing 100 $ more if i take in example the prize of graphics cards) will increase highly the performance of the G4 for intensive bandwitch applications ?

Comments

  • Reply 1 of 12
    applenutapplenut Posts: 5,768member
    [quote]Originally posted by powerdoc:

    <strong>If the next version of the G4 lack of DDR memory controller (in that case a larger L3 cache does not matter), don't you think they can get a larger L3 cache to improve the performance ?.



    The L3 cache is clocked at quarter speed (if we speak of real clock speed, and not the equivalent in clock speed like do Apple). A 1,2 ghz G4 will have a 300 mhz DDR L3 cache 128 bit wide. This kind of memory still exist in high end graphic card. 32 MB L3 cache already exist in the power 4.



    Don't you think that a 32 MB L3 cache (costing 100 $ more if i take in example the prize of graphics cards) will increase highly the performance of the G4 for intensive bandwitch applications ?</strong><hr></blockquote>





    I think it would cost a bit more than 100 dollars
  • Reply 2 of 12
    xypexype Posts: 672member
    [quote]Originally posted by powerdoc:

    <strong>A 1,2 ghz G4 will have a 300 mhz DDR L3 cache 128 bit wide. This kind of memory still exist in high end graphic card. 32 MB L3 cache already exist in the power 4.</strong><hr></blockquote>



    Whoa there! From what I know those 32 MB of cache would have to be on-chip which means the CPU itself would get bigger and thus more expensive to manufacture. Also think cache RAM and memory RAM are not the same so you can't compare them.
  • Reply 3 of 12
    powerdocpowerdoc Posts: 8,123member
    [quote]Originally posted by xype:

    <strong>



    Whoa there! From what I know those 32 MB of cache would have to be on-chip which means the CPU itself would get bigger and thus more expensive to manufacture. Also think cache RAM and memory RAM are not the same so you can't compare them.</strong><hr></blockquote>



    I dont think that the current L3 cache is on chip, it's the L2 cache that is on chip.
  • Reply 4 of 12
    programmerprogrammer Posts: 3,409member
    I doubt the L3 cache will get bigger -- its too expensive. If we see a new G4, I really hope that they remove the L3 completely and increase the size of the on-chip L1 and/or L2 caches, as well as speed up the bus. If the bus doesn't receive a significant speed bump then the L3 will stay in its current form, I expect. If it does and a process shrink to 0.13 finally happens then they can probably double the L2 cache size.



    The L3 is expensive for a couple of reasons -- the high speed external memory being the obvious one. The huge number of pins needed to connect it is another. The on-chip L3 cache controller and all the cache tags is a third. If they remove it and process shrink then the new chips could get a better yield, have much larger/faster onchip caches, and be cheaper on boards that are easier to build. Win win win win.
  • Reply 5 of 12
    powerdocpowerdoc Posts: 8,123member
    [quote]Originally posted by Programmer:

    <strong>I doubt the L3 cache will get bigger -- its too expensive. If we see a new G4, I really hope that they remove the L3 completely and increase the size of the on-chip L1 and/or L2 caches, as well as speed up the bus. If the bus doesn't receive a significant speed bump then the L3 will stay in its current form, I expect. If it does and a process shrink to 0.13 finally happens then they can probably double the L2 cache size.



    The L3 is expensive for a couple of reasons -- the high speed external memory being the obvious one. The huge number of pins needed to connect it is another. The on-chip L3 cache controller and all the cache tags is a third. If they remove it and process shrink then the new chips could get a better yield, have much larger/faster onchip caches, and be cheaper on boards that are easier to build. Win win win win.</strong><hr></blockquote>

    I agree that a speed up of the Bus will be the best. But has you have said before, there is little chance that we will see DDR Mpx bus. So this increase of L3 was a trick to improve the performances in the lack of the next logical step in the G4 design.



    Does a 250 mhz DDR ram L3 cache cost more than 250 Mhz DDRam graphic memory ? : i mean is it the same memory or an another ? : if the same it's not that expansive, in the contrary there will never a so huge L3 cache.
  • Reply 6 of 12
    xypexype Posts: 672member
    [quote]Originally posted by powerdoc:

    <strong>



    I dont think that the current L3 cache is on chip, it's the L2 cache that is on chip.</strong><hr></blockquote>

    Duh, my bad. But then, isn't it also a question of mere space? I mean L3 needs to be placed near the CPU and 64 MB might be big in the sense of pins connected, or?



    Also, thought 32 mb of L3 cache would be uber-cool, how are the chances for it to fail? With normal PC DDR memory I heard quite a few stories of "memory failing" (even brand memory), is L3 memory at same "risk" of failing as normal memory? And if so, wouldn't such a fialure render the computer unusable?
  • Reply 7 of 12
    The 7455 uses DDR SRAM for its L3 cache, graphics cards and main memory use DDR SDRAM. SRAM is alot more expensive than SDRAM.



    [ 06-15-2002: Message edited by: Analogue bubblebath ]</p>
  • Reply 8 of 12
    programmerprogrammer Posts: 3,409member
    [quote]Originally posted by powerdoc:

    <strong>

    I agree that a speed up of the Bus will be the best. But has you have said before, there is little chance that we will see DDR Mpx bus. So this increase of L3 was a trick to improve the performances in the lack of the next logical step in the G4 design.



    Does a 250 mhz DDR ram L3 cache cost more than 250 Mhz DDRam graphic memory ? : i mean is it the same memory or an another ? : if the same it's not that expansive, in the contrary there will never a so huge L3 cache.</strong><hr></blockquote>



    Motorola has said MPX may accelerate to 166 MHz, and we don't know the benefits of feeding MPX from DDR memory yet (there might be some). This could net 25-30% bandwidth improvement. Double the size of the L2 cache and increase the processor's clock rate to &gt;1.2 GHz and an L3 cache is making less sense that before -- certainly if probably wouldn't pay off to make it even bigger since that would require further redesign of the processor.
  • Reply 9 of 12
    powerdocpowerdoc Posts: 8,123member
    Well you are probabily right : it will be more simple for Mot to develop a DDR memory interface and larger L2 cache than a very large L3 cache.

    But i have doubt concerning the 166 mhz memory : is it less or more expansive than DDR memory at 133 mhz ?
  • Reply 10 of 12
    zosozoso Posts: 177member
    [quote]Originally posted by powerdoc:

    <strong>But i have doubt concerning the 166 mhz memory : is it less or more expansive than DDR memory at 133 mhz ?</strong><hr></blockquote>



    166 MHz memory is usually called PC2700, or DDR 333 (166 x 2). Low-latency samples (CL2) are far more expensive than PC2100, aka DDR 266 (133 x 2). Higher-latency parts, such as CL2.5 or CL3, offer little or no performance benefit when compared to CL2 DDR266 memory, but at a higher cost.



    As we can see--on the Mac pltaform--in the Xserve, memory clock and FSB can easily be asynchronous: in this particular case, the FSB runs at 133 MHz SDR, while the memory bus doubles that figure, running at 266 MHz DDR. In this scenario the problem is that it looks like the 2 CPUs, limited by the narrow bandwidth of the FSB, won't directly benefit that much from the faster memory. It's still a big improvement though, because Direct Memory Access devices can access Ram without stealing bandwidth from the CPUs.



    I think that by "MPX bus at 166 MHz" people in this thread are referring to SDR speed figures. Otherwise it'd mean DDR333--which is something I'd really want to see on a Mac, but I'm not holding my breath right now. As has been proved, the MPX bus protocol is very efficient, providing a much higher sustained transfer rate than a regular Wintel PC133 FSB. So, 33 more MHz added to the MPX wouldn't be astonishingly great--but the CPU(s) would no doubt benefit a lot from the increased bandwidth.



    I hope I understood your question--if you were just talking about DDR333 memory prices please disregard everything beyond the first paragraph...



    ZoSo
  • Reply 11 of 12
    powerdocpowerdoc Posts: 8,123member
    [quote]Originally posted by ZoSo:

    <strong>



    166 MHz memory is usually called PC2700, or DDR 333 (166 x 2). Low-latency samples (CL2) are far more expensive than PC2100, aka DDR 266 (133 x 2). Higher-latency parts, such as CL2.5 or CL3, offer little or no performance benefit when compared to CL2 DDR266 memory, but at a higher cost.



    As we can see--on the Mac pltaform--in the Xserve, memory clock and FSB can easily be asynchronous: in this particular case, the FSB runs at 133 MHz SDR, while the memory bus doubles that figure, running at 266 MHz DDR. In this scenario the problem is that it looks like the 2 CPUs, limited by the narrow bandwidth of the FSB, won't directly benefit that much from the faster memory. It's still a big improvement though, because Direct Memory Access devices can access Ram without stealing bandwidth from the CPUs.



    I think that by "MPX bus at 166 MHz" people in this thread are referring to SDR speed figures. Otherwise it'd mean DDR333--which is something I'd really want to see on a Mac, but I'm not holding my breath right now. As has been proved, the MPX bus protocol is very efficient, providing a much higher sustained transfer rate than a regular Wintel PC133 FSB. So, 33 more MHz added to the MPX wouldn't be astonishingly great--but the CPU(s) would no doubt benefit a lot from the increased bandwidth.



    I hope I understood your question--if you were just talking about DDR333 memory prices please disregard everything beyond the first paragraph...



    ZoSo</strong><hr></blockquote>

    I was speaking of 166 mhz single Sdram memory. But you made a good point even with only with the current MPX front bus boosted at 166 mhz, the mobo can use DDR memory like the I Serve.

  • Reply 12 of 12
    [quote]Originally posted by ZoSo:

    As we can see--on the Mac platform--in the Xserve, memory clock and FSB can easily be asynchronous: in this particular case, the FSB runs at 133 MHz SDR, while the memory bus doubles that figure, running at 266 MHz DDR.<hr></blockquote>



    Actually, both those busses run at 133 MHz, but the memory bus uses DDR technology, hench the 266 MHz effective data rate. Now the L3 Cache bus really is running at 266MHz for an effective data rate of 532 MHz.
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