Apple, TSMC reportedly ramping up 10nm chip mass production for use in future iPhones

Posted:
in iPhone
Reports from China suggest that the major chip fabricators are all readying mass production of 10nm process processors, including Apple's manufacturing partner TSMC for multiple companies.




According to supply chain reports from DigiTimes besides just for Apple's future A-series processors, TSMC will supply the Helio X30 and X35 for MediaTek, between the end of 2016 and 2017.

TSMC is also expected to provide chips for HiSilicon, which will ultimately find its way into Android-based Huawei flagship phones.

Apple's A10 Fusion chip as found in the iPhone 7 family utilizes TSMC's 16nm FinFET process. Apple's A9 in the iPhone 6S family and iPhone SE, and A9X processors found in the 12.9-inch iPad Pro use the same size die.

Two otherwise identical chips with different die sizes have less the current used on the chip manufactured with the smaller die. As a result, in most cases the generated heat is less, and the power demanded by the smaller die size chip is lower as well.

Qualcomm has also recently announced its 10nm mobile chips will be fabricated by Samsung, with shipment of the Snapdragon 835 in commercial devices in the first half of 2017. Samsung's as-yet unrevealed Exynos evolution is also expected in the first half of 2017.

Smaller die sizes are in development at this point. IBM has built the first functional chips with 7nm technology, with consumer products with the technology likely at some point in 2019.

Comments

  • Reply 1 of 9
    wood1208wood1208 Posts: 1,712member
    Nothing new. 10nm A11 is destined for iPhone 7s or 8 whatever Apple will choose to call. Surprise can be if next iPad upgrade has A10X shrunk to 10nm for extra performance, efficiency and less power consumption..
    edited November 2016 cali
  • Reply 2 of 9
    It's worth noting that almost all process geometry labels these days (7nm, 10nm, 14nm, etc.) are pure marketing hype. The "rationale" for this is that they've made other manufacturing improvements (better FinFet, etc.) that give them performance / efficiency increases that would traditionally be associated with a real shrink, but the actual shrinks are much less than what they are telling people. This means that while things are improving, die sizes are not actually getting nearly as much smaller as the process geometry labels suggest, and die size is one of the major driving factors of cost. So while things are clearly getting better, we're also going to pay disproportionally more for each new generation of improvement. 
    perkedel
  • Reply 3 of 9
    Apple's A9 uses 16FF whereas A10 uses 16FFC.  FFC reduced the size of the underlying metal layer.

    In 16FF the transistor went to TSMC's 16NM node but the metal layer connections were still from the 20NM node.  So you have faster and more power efficient transistors on top of a larger spaced connectivity grid.  In FFC, the designers could put those transistors closer together if they wanted to.  Designers space transistors differently depending on power and heat, crosstalk, etc.  The efficiency cores running at a lower speed are probably more tightly spaced taking advantage of the new metal layer.

    So you should consider the 2016 A10 as a further shrink in process node.  TSMC's 10NM node will be a shrink of both the transistor and the underlying wiring in one generation.  
  • Reply 4 of 9
    The only thing I give 2 shits about is that it is TSMC who has manufacturing in the US. Hopefully they will continue to invest.
    watto_cobrajcs2305perkedel
  • Reply 5 of 9
    smalmsmalm Posts: 654member
    Apple's A9 uses 16FF whereas A10 uses 16FFC.  FFC reduced the size of the underlying metal layer.

    In 16FF the transistor went to TSMC's 16NM node but the metal layer connections were still from the 20NM node.   
    Apple' A9 uses 16FF+ which already has the reduced metal layer pitch - FCC is more about reduced development compexity and production effort.
  • Reply 6 of 9
    wizard69wizard69 Posts: 12,656member
    wood1208 said:
    Nothing new. 10nm A11 is destined for iPhone 7s or 8 whatever Apple will choose to call. Surprise can be if next iPad upgrade has A10X shrunk to 10nm for extra performance, efficiency and less power consumption..
    I'd love to see this happen for the next iPad update.   However it isn't a simple as it sounds, you have to manufacture a die to a certain areal size simply to allow room for i/O bonding pads.   It is TSMC stacked die process that puts na interesting spin on this issue.
  • Reply 7 of 9
    wizard69wizard69 Posts: 12,656member
    Apple's A9 uses 16FF whereas A10 uses 16FFC.  FFC reduced the size of the underlying metal layer.

    In 16FF the transistor went to TSMC's 16NM node but the metal layer connections were still from the 20NM node.  So you have faster and more power efficient transistors on top of a larger spaced connectivity grid.  In FFC, the designers could put those transistors closer together if they wanted to.  Designers space transistors differently depending on power and heat, crosstalk, etc.  The efficiency cores running at a lower speed are probably more tightly spaced taking advantage of the new metal layer.

    So you should consider the 2016 A10 as a further shrink in process node.  TSMC's 10NM node will be a shrink of both the transistor and the underlying wiring in one generation.  
    Process refinement at a "node" size isn't uncommon at all. To some extent or another all manufactures do this. This doesn't even take into account process optimization for different goals. Many manufactures have a low power process and a high performance process at each node.
  • Reply 8 of 9
    wizard69wizard69 Posts: 12,656member
    The only thing I give 2 shits about is that it is TSMC who has manufacturing in the US. Hopefully they will continue to invest.
    That would be Samsung, I don't know of any TSMC plants in the USA.   I'd love to see such of course.    
    perkedel
  • Reply 9 of 9
    The author in this article is getting some basic terminology wrong. He incorrectly uses the term "die size" in place of "feature size". Smaller feature size allows one to pack more transistors in a given area and thus reduce the size of the chip with a given design and transistor count. In other words, it can reduce die size.

    This is a tech based site. As a long reader since this site was founded over 20 years ago, I expect AI writers to get the basics right. 
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