What kind of a motherboard would the G5 have?
Motoman said that the G5 WOULD be based on RapidIO vs. MPX and 60x and have it's own memory controller. I've read up on RIO and it shows great bandwith by using serial connections to chips at moderate bit lenght (8-16bits wide) and high speeds (400-1GHz). It also has the ability to double pump. In this case Apple could situate their brand new G5 processor on a motherboard with a connection to the peripheral controller (PCI, ethernet, firewire, ATA, USB, sound, AGP) with tremendous bandwidth. How great? Well starting at 400MHz, 16bit, full duplex operation(transfer at rising and falling clock cycle) you get 12Gbps or 1.6GBps. Mind you we are at 133MHz 64 bit which translates to 1.0GBps. Not too shabby for RIO... until you factor in that the G5 will have 2 RIO ports! That's a combined 3.2GBps! 3 fold over what we have now! And it scales! The website (rapidio.org) states the spec lets it scale to 1GHz speeds and that's 60Gbps or 8GBps times 2 = 16GBps! This is off to the future but you get the point on scalability.
Amazing.... until you again factor in that the G5 will have it's own memory controller. Now I'm not 100% sure on this one but every description of the G5 so far has included it and the memory controller on the 8540 embedded G5 motorola announced includes a DDR333 controller (64bit wide I think). That in itself would be condusive to blistering memory access as it would be on it's own bus and would not have to sync to a system bus. Think about it. It has a 64bit pipe to the DDR DIMMS but internally the controller can connect to the processor core at 128 or even 256bits. That leaves RIO with 3.2GBps bandwidth for AGP4/8x, PCI64 or PCI-X bus, ATA, sound, 1394b, and Gb ethernet. And they'll need it.
What do I think the next motherboard will have?
* 400MHz system bus to Pangea chip
* 3/4 DDR PC2100 or PC2700 DIMM slots
* 4 PCI-X slots
* AGP4X Pro
* Firewire 1394b
* ATA/133
* USB 1.1
* Gb Ethernet
I hope these specs are true.
Amazing.... until you again factor in that the G5 will have it's own memory controller. Now I'm not 100% sure on this one but every description of the G5 so far has included it and the memory controller on the 8540 embedded G5 motorola announced includes a DDR333 controller (64bit wide I think). That in itself would be condusive to blistering memory access as it would be on it's own bus and would not have to sync to a system bus. Think about it. It has a 64bit pipe to the DDR DIMMS but internally the controller can connect to the processor core at 128 or even 256bits. That leaves RIO with 3.2GBps bandwidth for AGP4/8x, PCI64 or PCI-X bus, ATA, sound, 1394b, and Gb ethernet. And they'll need it.
What do I think the next motherboard will have?
* 400MHz system bus to Pangea chip
* 3/4 DDR PC2100 or PC2700 DIMM slots
* 4 PCI-X slots
* AGP4X Pro
* Firewire 1394b
* ATA/133
* USB 1.1
* Gb Ethernet
I hope these specs are true.
Comments
Good post.
<strong>THIS IS MY FIRST POST SO BE KIND, I'VE HEARD FROM A FRIEND WHO WORKS AT AN APPLE DEALER, THAT THE RAM WILL BE DDR, HE ALSO SAID IT WOULD OPERATE AT 266MHZ, THAT'S ALL I KNOW, HE SAID THAT HE HEARD IT FROM HIS MEMORY VENDOR.</strong><hr></blockquote>
You must be new to computers as well, on the left hand side of the keyboard (I assume you know what that is) there is a key called Caps Lock (above the shift key), make sure the little green light is not on, OR YOU MAKE YOURSELF LOOK LIKE A TWIT. And remember, setting a body of text in ALL-CAPS is a beginners mistake that only serves to reduce the readability of what you are trying to say, as all the words have the same shape.
edit: DAMN SOMEONE BEAT ME TO IT!!!!!!
[ 12-14-2001: Message edited by: MarcUK ]</p>
<strong>Motoman said that the G5 WOULD be based on RapidIO vs. MPX and 60x and have it's own memory controller. I've read up on RIO and it shows great bandwith by using serial connections to chips at moderate bit lenght (8-16bits wide) and high speeds (400-1GHz). It also has the ability to double pump. In this case Apple could situate their brand new G5 processor on a motherboard with a connection to the peripheral controller (PCI, ethernet, firewire, ATA, USB, sound, AGP) with tremendous bandwidth. How great? Well starting at 400MHz, 16bit, full duplex operation(transfer at rising and falling clock cycle) you get 12Gbps or 1.6GBps. Mind you we are at 133MHz 64 bit which translates to 1.0GBps. Not too shabby for RIO... until you factor in that the G5 will have 2 RIO ports! That's a combined 3.2GBps! 3 fold over what we have now! And it scales! The website (rapidio.org) states the spec lets it scale to 1GHz speeds and that's 60Gbps or 8GBps times 2 = 16GBps! This is off to the future but you get the point on scalability.
Amazing.... until you again factor in that the G5 will have it's own memory controller. Now I'm not 100% sure on this one but every description of the G5 so far has included it and the memory controller on the 8540 embedded G5 motorola announced includes a DDR333 controller (64bit wide I think). That in itself would be condusive to blistering memory access as it would be on it's own bus and would not have to sync to a system bus. Think about it. It has a 64bit pipe to the DDR DIMMS but internally the controller can connect to the processor core at 128 or even 256bits. That leaves RIO with 3.2GBps bandwidth for AGP4/8x, PCI64 or PCI-X bus, ATA, sound, 1394b, and Gb ethernet. And they'll need it.
What do I think the next motherboard will have?
* 400MHz system bus to Pangea chip
* 3/4 DDR PC2100 or PC2700 DIMM slots
* 4 PCI-X slots
* AGP4X Pro
* Firewire 1394b
* ATA/133
* USB 1.1
* Gb Ethernet
I hope these specs are true.</strong><hr></blockquote>
Unfortunately, the full duplex doesn´t mean it´s double pumped (two data items per clock), just bidirectional, ie. it can transfer data at full speed in both directions simultaneously. It is also currently a parallel bus, in that the data streams share a clock sgnal etc.
It is also important to distinguish what Motorola choose to put in an embedded chip from what will be in the G5, and to note that the 8450 is not due out till the second half of next year. Whilst I certainly hope that the G5 will have onboard memory controller(s), I seriously doubt they will debut at 333MHz, because that memory is not yet widely available or cheap, and Apple tend to be somewhat conservative in the memory specs. Putting the memory controller on-chip (as per AMD´s Hammer series) seriously improves memory latency, although not significantly affecting bandwidth, however going to DDR266 will double the bandwidth from the current SDR133 straight off. They could double the bandwidth again by going to dual channel (128 bit wide) memory, but this would require memory to be added in pairs of DIMMs always, and might not give such a huge boost if it doesn´t match the L2 line width properly.
Personally, I suspect that the G5 will have a Hypertransport bus (or 2) running at a full duplex, double pumped 400MHz, probably 16 bits wide, but possibly 32 (although that requires about 200 pins per bus, which would rule out 2 busses). Hypertransport southbridges are already available (eg: nVidia´s MCP) as are some of the individual PCI/AGP/etc. bridge chips.
Michael
Also i checked pricewatch.com and they have 14 listings for PC2700 256MB DIMMS going for between $67 and $105 each. No too bad considering prices of PC2100 are going for $45-$117. They could possibly use it to their advantage in marketing terms. it would also boost production of PC2700 as PC manufacturers would scramble to include PC2700 support in their computers. This way they could use a cheaper 64bit bus to memory so you can add one DIMM at a time and still get superior performance and for a short while anyway, be ahead of PC's.
<strong>RIO is going to be used on the G5 but i wonder if they'll piggyback the hyperTransport protocol on the RIO bus. Is this possible? </strong><hr></blockquote>
Unfortunately not, the two busses overlap considerably in function, but as I understand it Motorola are committed to RapidIO in the embedded versions of the G5 family, they haven´t said anything yet about the 8500, presumably Apple wont let them. Apple have, however, signed up to the Hypertransport group.
[quote]
<strong>
Also i checked pricewatch.com and they have 14 listings for PC2700 256MB DIMMS going for between $67 and $105 each. No too bad considering prices of PC2100 are going for $45-$117. They could possibly use it to their advantage in marketing terms. it would also boost production of PC2700 as PC manufacturers would scramble to include PC2700 support in their computers. This way they could use a cheaper 64bit bus to memory so you can add one DIMM at a time and still get superior performance and for a short while anyway, be ahead of PC's.</strong><hr></blockquote>
SiS already have a DDR333 capable chipset for the Pentium4, although I´m not aware of any boards available yet. Dual channel would be nicer, the bandwidth would be phenomenal, just what you need for streaming video encoding/decoding and especially for applying effects in real time to audio and possibly video.
On another note, what I would like to see in the chip itself is 256 bit wide Altivec with 64 bit floating point capacity, but I don´t expect that until the G6. I suspect they must have put in some more fpu units to pump up it's performance, and increased the issue width. I have to admit to being primarily interested in engineering code, double precision floating point performance is everything.
Michael
The motorola roadmap say that the G5 series will have RIO and I think that will include any G5 that Apple would use in their systems. Now unless Apple takes complete control over the desktop version of the G5 design and incorporates HT into it, we probably will be seeing an implimentation of RIO on the Apple motherboards. Maybe Apple intends to use HT as a bridge between PCI devices and the main controller? Who knows. And we won't find out until a week after the new machines are out in a developer note or TIL. Either route (RIO or HT) it will be more advanced than what we have now.
BTW, how does the nVidea chipset use HyperTransport? I thought it was merely between the North bridge and South bridge and the North bridge interacted between it and the processor through Intels x86 processor bus.
<strong>I have a feeling that Motorola is trying to beef up Altivec and get rid of a dedicated FPU all together. That would mean they need powerful FPUs in Altivec and make it transparent to compilers. I don't think this is hard to do since Intel was trying to get THEIR developers to do the same with SSE2.</strong><hr></blockquote>
Yes, a fine thing to try, just that nasty backward compatibility thing to trip you up. All PPC code assumes an FPU will be available (Not that it all actually uses it) so you can't get rid of it. Intel have considerable problems with the P4 because it's FPU is underpowered compared to the AMD offering because SSE2 is there, but it is very difficult to recode most FPU intensive code to use the SSE2 units to give any siignificant speed-up at the moment, compiler technology for auto vectorisation simply isn't up to it yet (and that's Intel compilers which are way ahead of the gcc that Apple has in OSX). Believe me, I'm looking into threading and vectorising some of my code right now and it is very difficult since mostly it deals with unstructured sets of data, some speed-up is certainly possible, but I'd do very evil things for a faster FPU. If the G5 is anything like the rumours I may persuade my (agent/dealer/boss) to let me release the Mac version at last.
[quote]<strong>
The motorola roadmap say that the G5 series will have RIO and I think that will include any G5 that Apple would use in their systems. Now unless Apple takes complete control over the desktop version of the G5 design and incorporates HT into it, we probably will be seeing an implimentation of RIO on the Apple motherboards. Maybe Apple intends to use HT as a bridge between PCI devices and the main controller? Who knows. And we won't find out until a week after the new machines are out in a developer note or TIL. Either route (RIO or HT) it will be more advanced than what we have now.
</strong><hr></blockquote>
Could well be, exciting, we will have to wait and see.
[quote]<strong>
BTW, how does the nVidea chipset use HyperTransport? I thought it was merely between the North bridge and South bridge and the North bridge interacted between it and the processor through Intels x86 processor bus.</strong><hr></blockquote>
Yes, quite true, (except its the EV6 bus for the AMD version of the chipset, Pentium bus for the X-box) but does the G5 need a Northbridge? Most Northbridges just do memory access and graphics, you can attach a Hypertransport to AGP bridge for the graphics and that's it.
As far as nVidia are concerned the big advantage is that they have enough bandwidth to cope with several PCI(-X) busses and the other peripherals, which they would'nt were thay to use the more traditional PCI link between the north and south bridges.
<strong>
Most Northbridges just do memory access and graphics, `````````` to use the more traditional PCI link between the north and south bridges.</strong><hr></blockquote>
Gotta ask ...
Whatsa Northbridge, Whatsa southbridge?
<img src="confused.gif" border="0">
[CPU]
|
[NB]---[PCI slots]
|
[SB]---[ATA]
|
[USB and othe ports]
This is how a typical PC would look like. (above)
<strong>
Gotta ask ...
Whatsa Northbridge, Whatsa southbridge?
</strong><hr></blockquote>
from Sharkyextreme
The northbridge communicates with the CPU over the Front Side Bus (FSB) and acts as the controller for memory, AGP and PCI. The type of FSB, memory and AGP varies from northbridge to northbridge. Some northbridges integrate video as well.
The southbridge takes care of most basic forms of I/O, such as USB, serial ports, audio, IDE and more. What I/O is controlled depends on the specific southbridge. The southbridge sits on the northbridge's PCI bus, which is usually a 32-bit, 33MHz bus capable of providing 133MBps of bandwidth.
/edit/ DOH Outsider you already beat me to it
[ 12-15-2001: Message edited by: ZO ]</p>