Memory bandwidth on future PowerPCs
I've been reading up on the POWER4 architecture and have found that it is highly optimized for bandwidth (duh). IBM went to great lengths to make sure the POWER4 would be fed from memory at all times and have memory access across processors (and MMCs) with a high memory bandwidth. See this graphic and note how the POWER4 accesses memory:
<a href="http://www.digit-life.com/articles/ibmpower4/"; target="_blank">
</a>
click image for link to article
notice a GX bus that runs at 1/3 the processor core speed and at 32bit. On a 1GHz core this only yields 1.6GBps, far short of the proposed 6.4GBps that IBM's new POWER4 derivative PowerPC processor is supposed to have. but notice that the actual memory bus is piggy backed on the L3 cache bus. This was odd to me at first, but what if IBM has done this to use the shared cache features of its SMP design and applied it to the main memory? That way the other processors in an MP configuration could share main memory from the external memory controller on another processor just as easily as it snoops another L3 cache. The POWER4 uses a separate bus between MMC's to handle cross memory accesses, and I think this can be done simply with a fast RIO bus (albeit with a hit in performance but not any worse than the present situation). Or the GX bus can be used for his while leaving a RIO bus for the PCI/peripheral bus. Either way this is far more adaptive than anything and advanced we see now in the Mac world OR PC world.
[ 08-09-2002: Message edited by: Outsider ]</p>
<a href="http://www.digit-life.com/articles/ibmpower4/"; target="_blank">
</a>click image for link to article
notice a GX bus that runs at 1/3 the processor core speed and at 32bit. On a 1GHz core this only yields 1.6GBps, far short of the proposed 6.4GBps that IBM's new POWER4 derivative PowerPC processor is supposed to have. but notice that the actual memory bus is piggy backed on the L3 cache bus. This was odd to me at first, but what if IBM has done this to use the shared cache features of its SMP design and applied it to the main memory? That way the other processors in an MP configuration could share main memory from the external memory controller on another processor just as easily as it snoops another L3 cache. The POWER4 uses a separate bus between MMC's to handle cross memory accesses, and I think this can be done simply with a fast RIO bus (albeit with a hit in performance but not any worse than the present situation). Or the GX bus can be used for his while leaving a RIO bus for the PCI/peripheral bus. Either way this is far more adaptive than anything and advanced we see now in the Mac world OR PC world.
[ 08-09-2002: Message edited by: Outsider ]</p>
Comments
<strong>yawn. dude you really could have posted this in another thread discussing the power 4. <img src="graemlins/oyvey.gif" border="0" alt="[No]" /> </strong><hr></blockquote>
HEY NEWBIE! When we want your opinion we'll give it to you.....heheh just kidding.
I think this is an important distinction that merits it's own thread.
I'm sure they'll be lot's of good info here.
<strong>
HEY NEWBIE! When we want your opinion we'll give it to you.....heheh just kidding.
I think this is an important distinction that merits it's own thread.
I'm sure they'll be lot's of good info here.</strong><hr></blockquote>
omfg n00b rofl tahts bs die plz kthxbye
<strong>
omfg n00b rofl tahts bs die plz kthxbye</strong><hr></blockquote>
Werd!
Doesn't the Power4 have a 400mhz Memory Bus? I wonder if that is changing with this new proc.
Has IBM joined Hypertransport? Grrrrrrrrr Oct can't come soon enough.