question - multiple core designs

in Future Apple Hardware edited January 2014
i thought about the opportunity for apple to get ibm to produce 970-like cpus with two cores. would this be cheaper for dual-machines like the current high end? also - would one of these cpus have two busses for each core or one shared bus? if it'd be a shared bus there would be a performance-disadvantage when comparing it to two single-core cpus wouldn't it?


another thought: would it be an advantage to have more altivec-units or would it be better to add another integer and floating point unit? is it possible to have a design in which two cores implement only the integer and floating point units and another "core" would implement a highly optimized version of altivec?


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    zapchudzapchud Posts: 844member
    Dual core-versions of the chip is possible, and would result in a substansial performance-boost over single-processor systems. In comparision to dual-processor machines, I don't know for sure, since the two cores would stay very close to each other, being able to communicate and cooperate effectively, but I'd also believe they'd share the FSB, which results in a performance-degration (meaning performance could be pretty equal to standard DP-systems). I also suspect that the cost of producing dual-core versions would be significantly higher than producing two separate, single cores. I believe having read that you can't just stuff two arbitrary cores to each other, and make them a couple, you need to produce the cores as a couple from the start, and to make the dual-core chip working, you of course need both cores to be working. I might be totally wrong on this, though...

    I don't know if there is any point doing this now, and I believe it isn't, since none of the desktop-CPU-makers do this currently. Only expensive chips like the POWER4 have this currently, afaik.

    I don't think there's any point in making two altivec-units per chip, compared to optimizing the current, single one. One could expand it's flexibility, and double it's bitness, which would result in the same potential/theoretical performance-boost as double units, but with much less silicon.

    Putting the altivec on a separate core would not be a very good solution, because it'd result in increased dedication of the various execution-units, need for more, and again dedicated cache - in total, it would result in a chip-design with alot of wasted and dedicated silicon. Sure, it'd be nice to have an extra 512kB of L2 cache for the altivec-unit, but it would also be wasted silicon whenever there is heavy work going on in the scalar units. The integer and floating point units could always benefit from more cache, but if the extra transistors are spent on the altivec-chip, the scalar units would benefit very little from it. 1 MB L2 cache availiable for all the execution-units on the chip, or half availiable to the scalar units, and the rest availiable to altivec? Reduced flexibility.

    You'd also be in the need for extra load/store-units, cache, and additional circuitry to make this thing work, creating alot of redundancy, at the price of less flexibility.

    Added integer (especially, the integer units in the G5 are lacking) and floating point units is feasible, and better use of silicon, I think...
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