G5: In-Flight Instructions Explanation

big macbig mac
Posted:
in Current Mac Hardware edited January 2014
I've read a number of times that the 970 contains something like 216 "in-flight" instructions, while the G4 has less than 20. The problem is, I don't really know what type of instructions these are, what kind of extra functionality is provided. Now, I know, of course, that there is the PPC ISA (Instruction Set Architecture), and all PPC processors have to contain the core ISA. I imagine that these extra in-flight instructions are separate from the regular PPC ISA, correct?



Additionally, while I know these in-flight instructions are a positive development, it seems that it is a departure from the RISC design ethos. Didn't IBM originally reject Altivec partially because it detracted from RISC design? I realize that most say there's very little divide between RISC and CISC today, but I'm speaking more theoretically. The most important aspect of RISC design, as I understand it, is that the instructions should complete in optimally one cycle. As long as these new instructions aren't too complex, we're technically still talking about RISC, I imagine. And yet, the expansion of the instruction set seems to complicate rather than reduce the complexity of the chip. Would anyone care to expand my base of knowledge in this area?

Comments

  • Reply 1 of 4
    airslufairsluf Posts: 1,861member
    Kickaha and Amorph couldn't moderate themselves out of a paper bag. Abdicate responsibility and succumb to idiocy. Two years of letting a member make personal attacks against others, then stepping aside when someone won't put up with it. Not only that but go ahead and shut down my posting priviledges but not the one making the attacks. Not even the common decency to abide by their warning (afer three days of absorbing personal attacks with no mods in sight), just shut my posting down and then say it might happen later if a certian line is crossed. Bullshit flag is flying, I won't abide by lying and coddling of liars who go off-site, create accounts differing in a single letter from my handle with the express purpose to decieve and then claim here that I did it. Everyone be warned, kim kap sol is a lying, deceitful poster.



    Now I guess they should have banned me rather than just shut off posting priviledges, because kickaha and Amorph definitely aren't going to like being called to task when they thought they had it all ignored *cough* *cough* I mean under control. Just a couple o' tools.



    Don't worry, as soon as my work resetting my posts is done I'll disappear forever.
  • Reply 2 of 4
    shetlineshetline Posts: 4,695member
    Quote:

    Originally posted by Big Mac

    I've read a number of times that the 970 contains something like 216 "in-flight" instructions...



    I think you're misreading this as if there's a type of instruction called an "in-flight" instruction, and that there are 196 new instructions (on top of 20). That's not the case.



    Someone who's a better chip guru than I can probably explain this much better, but as far as I know saying that an instruction is "in flight" means that it's somehow cued up for simulataneous processing along other instructions. This makes the number of in-flight instructions a measure of the chip's capacity for parallel processing, not a count of different kinds of instructions.
  • Reply 3 of 4
    big macbig mac Posts: 480member
    Thanks so much for the informative replies.
  • Reply 4 of 4
    dfryerdfryer Posts: 140member
    In a modern CPU, more than one instruction can be on its way to completion at any one time. For example, an instruction to add two numbers involves moving the numbers into the addition circuits, doing the addition, and moving them back, in addition to the steps required to actually determine that an 'add' instruction is what has been asked for. A major advance in CPU design was the introduction of "pipelining": the CPU fetches one instruction (say, an "add" instruction) and then while that instruction is being processed somewhere "deeper" in the CPU, another instruction is being fetched. All the instructions that are currently being processed are considered "in-flight".



    In addition to pipelining, instructions that don't depend on each other can be executed in parallel - for instance, while one part of the CPU is adding or subtracting, another part can be executing instructions to move a number from one place to another (as long as the 'add' instruction and the 'move' instruction don't rely on each other). This enables efficient use of the CPU's circuits, as well as allowing the CPU to finish more than one instruction every clock cycle, despite the fact that any one instruction takes more than one clock cycle to process. This is called "superscalar execution", I think.



    Finally, in order to keep all these pipeline stages and execution units full, the G5 can "look ahead" and execute instructions out of the order that they appear in the code, as long as they're relatively independant of operations that are still being completed. The large number of in-flight instructions that the G5 can handle at any one time is a reflection on how much stuff it can keep track of when managing all this pipelined, superscalar, out-of-order instructionage.



    At least I think so.



    If you want to go on a geek binge, check out Hannibal's articles on CPU design on ArsTechnica.com .
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