2004: Bandwidth heaven

Posted:
in Future Apple Hardware edited January 2014
From <a href="http://news.com.com/2100-1001-982484.html?tag=fd_nbs_ent"; target="_blank">this News.com article</a>:



[quote] HyperTransport 2.0 will provide data transfers between chips at 20 gigabytes to 40 gigabytes per second, depending on the system architecture.<hr></blockquote>



This is up from HT's current capabilities of 6.4-12.8GB/s.



In other words, motherboard and processor-to-processor bandwidth is about to take off like a rocket. This will change the way personal computers are built in astonishing ways. SMP will become cheaper and much more effective.



Of course, if HT can do that, so can similar technologies, like, say, the bus that the 970 uses...



This, folks, is going to be glorious. And Apple's going to be there: They are, after all, sitting on the HT consortium.

Comments

  • Reply 1 of 7
    scottscott Posts: 7,431member
    Stick a date on that Amorph Early 200X where X=?
  • Reply 2 of 7
    amorphamorph Posts: 7,112member
    Where X=X.



    Depending on other things, and assuming that the HT consortium doesn't run into snags, we might see this in a PowerMac in early to mid 2004? Just a guess.
  • Reply 3 of 7
    thttht Posts: 3,017member
    They expect to release a specification, I presume the alpha document, this time next year. We would be lucky to see hardware in 2005 let alone 2004.



    Rambus Yellowstone is where it's at! I'd even bet Hypertransport 2.0 uses Yellowstone technology as a baseline.
  • Reply 4 of 7
    Well this is where Intel will be at by then:



    <a href="http://www.theinquirer.net/?article=7481"; target="_blank">10 gigahertz</a>
  • Reply 5 of 7
    sc_marktsc_markt Posts: 1,393member
    So does the 970 use HT or RapidIO? According to IBM's powerpc roadmap, it says RapidIO. There is nothing there about HT.



    <a href="http://www-3.ibm.com/chips/products/powerpc//rdmap/roadmap_small.jpg"; target="_blank">http://www-3.ibm.com/chips/products/powerpc//rdmap/roadmap_small.jpg</a>;
  • Reply 6 of 7
    outsideroutsider Posts: 6,008member
    The 970 uses a modified 6XX bus (same bus used on the PowerPC 620 and 630, not to be confused with the 60X bus that was used on the 601-G3 chips). It's neither RIO or HT. Now Apple's controller can use HyperTransport to connect to anyhtin as much as they want.
  • Reply 7 of 7
    nevynnevyn Posts: 360member
    [quote]Originally posted by Producer:

    <strong>Well this is where Intel will be at by then: (10 GHz) [/URL]</strong><hr></blockquote>



    That's the CPU's Hz.. but that article doesn't say anything about bandwidth, the topic. It does mention that the 10GHz chip's FSB will be 1020MHz, which, if it's a 64-bit straight-forward bus would be 8GB/s or so.



    One of the neat aspects of both HT and RIO is that they are _switched_ buses, which means (depending on the topology) part A can talk to part B at the maximum speed, _AND_ part C can talk to part D at the maximum speed. That means that 'total bandwidth' numbers can quickly get insanely high -&gt; good thing.



    According to IBM, the PPC 970's bus is 'two unidirectional point-to-point buses with 6.4GB/s of useful data bandwidth'. The one thing that is clear, is that it is NOT a version of the MPX bus, the one on the G4. The Power4's bus is called the 'GX' bus.



    I don't know enough to determine if the PPC970's bus is GX-like, HT-like, or RIO-like. It seems to match at least some criteria from all of them - there's quite a bit of overlap, none of them would be disappointing.



    IBM & Motorola are on the RapidIO Steering Committee.

    Apple, nVidia, AMD and many others are leaders in the HT crowd.



    It is _claimed_ that it is easy to have RapidIO devices and HT devices coexist in one box. I'm thinking we may well see that.
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