IBM introduced its POWER5
Quote:
Based on the previous POWER 4 family the POWER5 is a two-core processor with on- chip memory with just under 2MB of L2 cache and support for DDR 1 and DDR 2 memory.
Whereas previous POWER4's allowed for scaling up to a 32-way configuration without clustering, IBM says the POWER5 doubles that to 64-physical processors without clustering. The company says the chip's simultainous multi-threading also makes it look like 128-threaded processor cores. The chip is application compatible with POWER4 and POWER4+ systems but not pin compatible.
Based on the previous POWER 4 family the POWER5 is a two-core processor with on- chip memory with just under 2MB of L2 cache and support for DDR 1 and DDR 2 memory.
Whereas previous POWER4's allowed for scaling up to a 32-way configuration without clustering, IBM says the POWER5 doubles that to 64-physical processors without clustering. The company says the chip's simultainous multi-threading also makes it look like 128-threaded processor cores. The chip is application compatible with POWER4 and POWER4+ systems but not pin compatible.
http://www.internetnews.com/infra/article.php/3091601
It will be interesting to see if this is the same chip to find it's way into Apple boxes. The article does mention that "It's primarily SMP [Symmetric MultiProcessing] configuration that will go in the top to bottom of our systems including clustering.." So I'm assuming Blades at the "bottom".
Comments
It's interesting to note that the Power5 is starting out at 13 micron about the same time that 9 micron becomes available for the 970. Power5 isn't expected to go 9 micron until 2005 --- late by 970 standards but probably (?) about right for the very conservative server chip market. Power5 is for ultra high reliability, so it's meant to work. Newfangled technology is lower priority than just working.
I hope the 980 doesn't need to wait for the Power5 to go 9 micron before it becomes available (presumably first on 9 micron).
Anyone know more about the dates between these two chips: power5 and 980?
There's no public information, except of course for the detail that there will be a 970-like family of CPUs based on the POWER5.
When IBM first talked about the Power5 didn't they make it sound like it was designed to go into their whole line of Servers, meaning stuff that houses Xeons and soon the 970 (Stuff that a Power4 wouldn't fit into).
Similar to Apple Power Macs too.
The article also mentions that the Power5 will scale to 3 Ghz, although "..The company did not immediately disclose the chip's final debut speeds, Papermaster said the POWER5 would range between 1.6 GHz and 3 GHz over the life of the family... Speed is not a factor, Papermaster said. What we've found is that the main thing is to optimize the silicon investment, If you look at POWER5 the ability to multi-threading, that really allows customers to have flexibility and reliability."
"Shipping in mid-2004" ..3 GHz this summer.
I wonder if there is more then one version of the chip?
Originally posted by tink
The article also mentions that the Power5 will scale to 3 Ghz, although "..The company did not immediately disclose the chip's final debut speeds, Papermaster said the POWER5 would range between 1.6 GHz and 3 GHz over the life of the family... Speed is not a factor, Papermaster said. What we've found is that the main thing is to optimize the silicon investment, If you look at POWER5 the ability to multi-threading, that really allows customers to have flexibility and reliability."
Honestly, I think the main point that needs to be made is that they are saying it comes with a cooler (assumption, because of new power-management system), multi-cored chip. This will probably allow it to out-perform the POWER4 chip at the same clock speed.
Also, something else to chew on... When IBM orginally announced the 970, they said between 1.4 and 1.8 GHz (if I remember right). What happened? 1.6 - 2.0 GHz. I think that IBM is notorously conservative with their projections.
These are big chips.
Never mind them showing up in a mac near you.
http://maccentral.macworld.com/news/...=1066143401000
For now, don't expect the Power5 to be used outside of the commercial computing market. Even using a 0.13-micron copper SOI (Silicon On Insulator) manufacturing process, a single 276 million transistor Power5 chip measures 389 square millimeters?far larger than the 267 square millimeter Power4 and almost four times as large as a PowerPC 970.
Originally posted by tink
Owza!
These are big chips.
Never mind them showing up in a mac near you.
So if there is a single cored Power 5 (aka PPC 980 in here) with 1 MB L2 cache (instead of 1.9 MB) and no L3 controller then we are much more in the region of the 970 die size.
The question I'm most interested in is what are all those extra trannies for? They have the same # of cores, only .5 MB extra L2, and a little extra logic for SMT (Intel said it only cost them a small increase - 10-20%, I think - for 'hyperthreading' the P4) but the die has increased by 45%. Does this add up?
MM
Originally posted by tink
Owza!
These are big chips.
Never mind them showing up in a mac near you.
They're large, but they are also dual core with large L2 cache.
Originally posted by MartianMatt
So if there is a single cored Power 5 (aka PPC 980 in here) with 1 MB L2 cache (instead of 1.9 MB) and no L3 controller then we are much more in the region of the 970 die size.
The question I'm most interested in is what are all those extra trannies for? They have the same # of cores, only .5 MB extra L2, and a little extra logic for SMT (Intel said it only cost them a small increase - 10-20%, I think - for 'hyperthreading' the P4) but the die has increased by 45%. Does this add up?
I believe IBM said the SMT was 25% -- probably due to the larger register file sizes on the PowerPC and more extensive implementation. There is also this "FastPath" stuff which IBM was talking abou last year, and the on-chip memory controller.
Originally posted by Locomotive
Didn't IBM promise some low end PPC 970 servers? If so, are they overdue?
They aren't overdue and they are coming.
Quote: "NOVA HAS been to the Microprocessor Forum and captured this picture of POWER5 chief scientist Balaram Sinharoy holding this eight way POWER5 MCM with a staggering 144MB of cache. Sheesh Kebab!"
I've been looking at the image, and I'm speculating that the four inner chips are the CPUs (the slightly more squareish ones). Bear in mind that the Power 5s are supposed be dual-core chips, so "eight way" doesn't equal eight physically separate CPUs. The outer four, more rectangular looking chips, are probably the cache(s).
I can't even imagine how many pins/bgas this thing would have on the bottom, and I'm sure that heat would be an interesting factor as well. I would also guess that this configuration would probably run tens of thousands of dollars, if not into the 6 digit range.
*drools*
That is beautiful.
Originally posted by Cake
Wow! That's like pr0n for geeks!
That is beautiful.
Now I just have to figure out how to fit one in my Cube 8)
Originally posted by Chagi
I've been looking at the image, and I'm speculating that the four inner chips are the CPUs (the slightly more squareish ones). Bear in mind that the Power 5s are supposed be dual-core chips, so "eight way" doesn't equal eight physically separate CPUs. The outer four, more rectangular looking chips, are probably the cache(s).
I agree.
I can't even imagine how many pins/bgas this thing would have on the bottom, and I'm sure that heat would be an interesting factor as well. I would also guess that this configuration would probably run tens of thousands of dollars, if not into the 6 digit range.
It may have less than you think. The attachment of this whole 8 core system to the rest of the world is through a very high speed interconnect bus which is probably a packet-based narrow serial bus like HyperTransport, RapidIO, and the 970 FSB. Just much faster. There might also be more than 1 of them... say 4 so you can connect left, right, up and down.
On the other hand 4 on chip memory controllers do need to connect to their memory...
Originally posted by Bigc
With SMT aren't the four dual-cores suppose to look like 16-cpu's (8-real, 8-virtual) giving four MCM's tied together acting as 64-way?
I haven't seen full details on the Power 5 released yet, so I could only hazard a guess. You would be right, but this assumes that the hardware (and OS at a higher level) would actually be aware of the multi-core aspect of each CPU. I have a feeling this dual-core design is transparent.
For those that aren't familiar with it, Hyperthreading (TM) on the newest Intel P4s makes each single CPU system appear as having two processors in the Win2K and WinXP task managers. There aren't any dual processor P4 systems, because MP in Intel land = Xeon territory. While it may briefly look cool, I find this a bit misleading.
I'm not sure what IBM is doing with their "dual-core" idea for the Power 5, and I haven't had a chance to read up on the detailed stuff relating to the Power4 dual-core implementation (of which the "G5" is a single core variant).
Can someone step in here to explain a bit further?
L3 or L2 (I'm guessing L3)?
Originally posted by Eric_Z
What kind of cache is that anyway?
L3 or L2 (I'm guessing L3)?
The big external ones are L3.
Originally posted by Chagi
I haven't seen full details on the Power 5 released yet, so I could only hazard a guess. You would be right, but this assumes that the hardware (and OS at a higher level) would actually be aware of the multi-core aspect of each CPU. I have a feeling this dual-core design is transparent.
For those that aren't familiar with it, Hyperthreading (TM) on the newest Intel P4s makes each single CPU system appear as having two processors in the Win2K and WinXP task managers. There aren't any dual processor P4 systems, because MP in Intel land = Xeon territory. While it may briefly look cool, I find this a bit misleading.
I'm not sure what IBM is doing with their "dual-core" idea for the Power 5, and I haven't had a chance to read up on the detailed stuff relating to the Power4 dual-core implementation (of which the "G5" is a single core variant).
Can someone step in here to explain a bit further?
As I understand it, when IBM says that it is a dual coar CPU it means that the CPU has the circutry for 2 CPU cores that are interconnected on the silicone. This is different than Hyperthreading becouse there really are two physical "CPU" cores instead on one CPU with a "Virtual" core. Now, if IBM's version of Hyperthreading ( if forget the name) works in a similar manner to Intels, then 1 G5 processor would appear to the system as 4 CPU's (2 physical and 2 "virtual). Of course I could be totally wrong on this, I'm not a hardware expert.