Help me with my math...

Posted:
in Current Mac Hardware edited January 2014
The IBM PPC 970 has a frontside bus that is 1/2 the CPU clock rate.



So a 2000 mHz 970 communicates with the system controller at 1000 mHz.





The PC3200 SDRAM in this machine is 400 mHz, DDR and dual-channel.



I am missing that step to go from 800 mHz (400 DDR) to 1000 (frontside bus).



Is this the control bits overhead for cache snooping, etc? So the CPU->System Controller is 1000 mHz, and the System Controller - > SDRAM is 800 mHz? What about the 1600 mHz 970 - uses PC2700 DDR 333?



What am I missing here (feel free to make humiliating remarks)?



Thanks.

Comments

  • Reply 1 of 3
    powerdocpowerdoc Posts: 8,122member
    Quote:

    Originally posted by lundy

    The IBM PPC 970 has a frontside bus that is 1/2 the CPU clock rate.



    So a 2000 mHz 970 communicates with the system controller at 1000 mHz.





    The PC3200 SDRAM in this machine is 400 mHz, DDR and dual-channel.



    I am missing that step to go from 800 mHz (400 DDR) to 1000 (frontside bus).



    Is this the control bits overhead for cache snooping, etc? So the CPU->System Controller is 1000 mHz, and the System Controller - > SDRAM is 800 mHz? What about the 1600 mHz 970 - uses PC2700 DDR 333?



    What am I missing here (feel free to make humiliating remarks)?



    Thanks.




    The answer is in one word : asynchronous



    The memory bandwitch and the memory bus are different.

    This is a common feature even in the PC world

    The most asynchronous model is the dual one, where there is two independants bus able to communicate with the system controller at 8 GB/sec (total 16 GB/sec) while the RAM is limited to 6,4 GB/sec.
  • Reply 2 of 3
    lundylundy Posts: 4,466member
    Quote:

    Originally posted by Powerdoc

    The answer is in one word : asynchronous



    The memory bandwitch and the memory bus are different.

    This is a common feature even in the PC world

    The most asynchronous model is the dual one, where there is two independants bus able to communicate with the system controller at 8 GB/sec (total 16 GB/sec) while the RAM is limited to 6,4 GB/sec.




    So can the system controller drive 500 mHz SDRAM? IOW, could you put that in the dual 2gHz? I can't find any reference to this.
  • Reply 3 of 3
    eugeneeugene Posts: 8,254member
    Quote:

    Originally posted by lundy

    So can the system controller drive 500 mHz SDRAM? IOW, could you put that in the dual 2gHz? I can't find any reference to this.



    The FSB *is* subject to some kind of overhead. IBM said way back when that the 1.8 GHz PPC970's 900 MHz bus was capable of 6.4 GBps of bandwidth and not 7.2 GBps like you'd expect.
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