Eskimo - Some explanation please

bodhibodhi
Posted:
in Current Mac Hardware edited January 2014
Eskimo or anyone else thatis familiar with processor technology please explain the following:



On Motorola's site it states the following about the new G4's in the updated Power Macs:



- More block address translation registers - increased from 8 to 16 to support efficient embedded operating systems through high speed mapping of additional large blocks of data.



Can you explain the advantages of this? Also, has anyone figured out how many pipelines the new G4 is?

Comments

  • Reply 1 of 6
    marcukmarcuk Posts: 4,442member
    new g4 (7455) = 7 stages
  • Reply 2 of 6
    bodhibodhi Posts: 1,424member
    bump
  • Reply 3 of 6
    krassykrassy Posts: 595member
    [quote]Originally posted by Bodhi:

    <strong>

    - More block address translation registers - increased from 8 to 16 to support efficient embedded operating systems through high speed mapping of additional large blocks of data.



    Can you explain the advantages of this? Also, has anyone figured out how many pipelines the new G4 is?</strong><hr></blockquote>



    The block address translation registers helps map out memory to cache. (Info from *I++)



    [ 01-28-2002: Message edited by: Krassy ]</p>
  • Reply 4 of 6
    eskimoeskimo Posts: 474member
    [quote]Originally posted by Krassy:

    <strong>



    The block address translation registers helps map out memory to cache. (Info from *I++)



    [ 01-28-2002: Message edited by: Krassy ]</strong><hr></blockquote>



    Sorry Bodhi, Krassy's explanation is as good as anything I can come up with. I don't think this will have a real effect for Apple's products, the changes Motorola seemed to implement were mainly intended for embedded customers. A programmer or a EE would know a lot more about this than I do.



    Here's a quote a quick search on the term came up with:

    [quote]The PowerPC also offers an alternative translation from logical to physical that bypasses the TLB/hash-table paging mechanism. When a logical address is referenced, the processor begins the page lookup and, in parallel, begins an operation called block address translation(BAT). Block address translation depends on eight BAT registers: four data and four instruction. The BAT registers associate virtual blocks of 128K or more with physical segments. If a translation via the BAT registers succeeds, the page table translation is abandoned.



    <hr></blockquote>
  • Reply 5 of 6
    bodhibodhi Posts: 1,424member
    So this is something that will not show a significant performance difference?



    Okay then....Thanks Eskimo.



    Bodhi
  • Reply 6 of 6
    krassykrassy Posts: 595member
    [quote]Originally posted by Bodhi:

    <strong>So this is something that will not show a significant performance difference?



    Okay then....Thanks Eskimo.



    Bodhi</strong><hr></blockquote>



    i think this can of course lead to a performance increase. if i remember correctly this could increase the performance of the paging mechanism which is for moving pages of memory to cache. if you have tp move a larger datablock the increase from 8 to 16 translation registers would allow to move them with one step instead of two steps...
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