90nm vs. 130nm

Posted:
in Future Apple Hardware edited January 2014
Hey Guys,

I've been reading about how the second generation G5 will probably be sporting the new 90 nm chips. There's one thing that I don't understand. Does the smaller size improve processing speed? For example, if I have two machines, one with dual 2ghz 130nm chips, and another machine with dual 2ghz 90nm chips, will the 90nm chips be faster, or will there be no speed increases? I know that the 90nm will allow for higher clock frequencies, but what if the clock frequency where the same? Would they be the same speed? Please let me know about this, thanks guys.

Comments

  • Reply 1 of 18
    thttht Posts: 3,011member
    Quote:

    Originally posted by acappellajosh

    Does the smaller size improve processing speed? For example, if I have two machines, one with dual 2ghz 130nm chips, and another machine with dual 2ghz 90nm chips, will the 90nm chips be faster, or will there be no speed increases?



    There will be no performance increases. (Given that the 130nm and the 90nm have the same exact design.)
  • Reply 2 of 18
    outsideroutsider Posts: 6,008member
    I was hoping they would double the cache to 1MB. Looks like not until the next generation G5.
  • Reply 3 of 18
    Quote:

    Originally posted by THT

    There will be no performance increases. (Given that the 130nm and the 90nm have the same exact design.)



    I'm not sure if that statement is 100% correct given that it appears that (at a minimum) IBM is incorporating PowerTune. That implies that they may well have also made other changes to tune the design.



    That doesn't necessarily mean that the 90nm chip would be faster, but it will likely be different - but not by much. Add on the potential that they would increase on-chip cache, add a memory controller or direct support for HyperTransport, then we could see significant performance increases.



    All pure speculation of course.
  • Reply 4 of 18
    brussellbrussell Posts: 9,812member
    Quote:

    Originally posted by THT

    There will be no performance increases. (Given that the 130nm and the 90nm have the same exact design.)



    Couldn't a smaller design mean a faster chip (at the same frequency) because there's less distance to travel? OK, maybe not 8 seconds in Photoshop or something, but at least in theory?
  • Reply 5 of 18
    Smaller distances means the ability to operate at higher frequencies, which gives higher performance. Just shortening distances doesn't do anything if you don't send information across those distances any more frequently.



    With a process shrink like this usually at least increase the cache sizes, if not improve the other execution resources at the same time. There isn't any hard information yet so its all just speculation.
  • Reply 6 of 18
    thttht Posts: 3,011member
    Quote:

    Originally posted by BRussell

    Couldn't a smaller design mean a faster chip (at the same frequency) because there's less distance to travel? OK, maybe not 8 seconds in Photoshop or something, but at least in theory?



    Programmer pretty much explained it. But you can think of it this way.



    Computers are digital devices. That means information is in the form of 1s and 0s. It doesn't matter how small the transistors are or what technology they are built from, information is passed in the form of 1s and 0s. Ie, a rise in voltage or a drop in voltage across a transistor or bus is interpreted as a 1 or a 0 (on or off whatever, just 2 states). These voltage rises and drops are "regulated", or maybe it is coincides with, the frequency at which the circuitry operates. Information is only passed at the speed of the operating frequency. So if the speed of light could be magically broken and a 2 GHz PPC 970 processor was built with vacuum tubes and is the size of NYC, it'll still have the same performance as a 90nm one.



    PowerTune in all likelihood will degrade the performance of 90 nm 970. You can see the effects of power saving technology in the Power Mac G5. It wastes precious milliseconds to go from 1.3 GHz to 2.0 GHz when it determines that the performance is needed. A PM G5 with the bus slewing turned off will perform a little bit better than one with the power setting turned on.



    I think fabricating the 970 with PowerTune, it is necessary, is all that IBM should do with the chip, given the existence of a Power5 inspired 970. The 970fx will be around 60 sq mm and twice as cheap coming of the wafer than the 130 nm 120+ sq mm version. That means G5 eMacs, iBooks, iMacs and Powerbooks.



    A Power5 inspired 970 with SMT, 1 MB L2 cache and on-chip memory controller will be a 120+ sq mm chip at 90 nm. If it comes in late 04 or early 05, Apple is fine with the current 970 design. If it is going to be later than that, then a 1 MB L2 970 is necessary.
  • Reply 7 of 18
    Quote:

    Originally posted by acappellajosh

    Hey Guys,

    I've been reading about how the second generation G5 will probably be sporting the new 90 nm chips. There's one thing that I don't understand. Does the smaller size improve processing speed? For example, if I have two machines, one with dual 2ghz 130nm chips, and another machine with dual 2ghz 90nm chips, will the 90nm chips be faster, or will there be no speed increases? I know that the 90nm will allow for higher clock frequencies, but what if the clock frequency where the same? Would they be the same speed? Please let me know about this, thanks guys.






    They should pretty much have the same performance. However, The 90nm processor will produce less heat and require less power to operate. Allowing for smaller heat syncs, quieter fans, smaller and quieter cases and perhaps even, longer component life.
  • Reply 8 of 18
    telomartelomar Posts: 1,804member
    Quote:

    Originally posted by THT

    There will be no performance increases. (Given that the 130nm and the 90nm have the same exact design.)



    Actually the two chips have differences in designs. The 90 nm version has to deal with significant current leakage and as such adjusting layout and circuitry usage becomes necessary.
  • Reply 9 of 18
    nr9nr9 Posts: 182member
    Quote:

    Originally posted by Telomar

    Actually the two chips have differences in designs. The 90 nm version has to deal with significant current leakage and as such adjusting layout and circuitry usage becomes necessary.



    layout obviously has to be different but the logic circuit is the same.



    current leakage is reduced a lot because of SSOI.



    layout will affect your capacitances, leakage, inductances which will affect your propgation delay and therefore your frequency



    it will not affect performance at the same frequency.
  • Reply 10 of 18
    whats so disheartning about the whole situation is motorola's lack of performance when it comes to rolling out new chips.

    the 7447 chip JUST came out.

    it uses the 0.013um process a FIRST for motorolas powerpc line.

    by all accounts it runs MUCH cooler at a given clock fruequency then their last generation of chips.

    but they are WAY BEHIND!

    ibm is AT 0.09um,RIGHT NOW.

    just imagine if motorola had 0.09um g4 chips,how cool they would run.

    its a shame because when it wants to,and i dont think motorola has wanted to in a LONG time,motorola can design great chips.
  • Reply 11 of 18
    nr9nr9 Posts: 182member
    motorola should outsource fabrication to TSMC and UMC



    both companies have 9 layer 90nm processes. the extra layers should allow for a smaller die and decreased cost.
  • Reply 12 of 18
    programmerprogrammer Posts: 3,409member
    Quote:

    Originally posted by Nr9

    motorola should outsource fabrication to TSMC and UMC



    both companies have 9 layer 90nm processes. the extra layers should allow for a smaller die and decreased cost.




    Now this would make sense (as opposed to Nr9's insistance that IBM should do the same). Certainly more sense than Moto fabbing their own chips in their expensive buildings that are by all accounts in need of a good dusting. As it is they instead seem to have thrown their hat in with ... STM & Philips, is it? I can't remember exactly. But its the European crown, IIRC.
  • Reply 13 of 18
    motorola hasn't cared for a very long time. the writing was on the wall with regards to its relationship with apple LONG before most people knew it. i only know because of friends, but the whole relationship was written off years ago.
  • Reply 14 of 18
    telomartelomar Posts: 1,804member
    Quote:

    Originally posted by Nr9

    layout obviously has to be different but the logic circuit is the same.



    current leakage is reduced a lot because of SSOI.



    layout will affect your capacitances, leakage, inductances which will affect your propgation delay and therefore your frequency



    it will not affect performance at the same frequency.




    I never stated layout would effect performance all I stated is there were some sizable differences between the 90 nm processor and the 130 nm PPC970. What they are will become apparent after release.



    As for SSOI I wouldn't count on seeing it being used just yet.
  • Reply 15 of 18
    amorphamorph Posts: 7,112member
    Quote:

    Originally posted by Programmer

    Now this would make sense (as opposed to Nr9's insistance that IBM should do the same). Certainly more sense than Moto fabbing their own chips in their expensive buildings that are by all accounts in need of a good dusting. As it is they instead seem to have thrown their hat in with ... STM & Philips, is it? I can't remember exactly. But its the European crown, IIRC.



    STM and Philips Semiconductor it is. Crolles is good for 90nm on down.



    So they've done what Nr9 (and, really, everyone) thinks they should do, although they've chosen different partners than he would have.



    That said, Motorola does outsource a lot to TSMC and UMC. They make all the parts at processes bigger than 180nm. They're what enabled Motorola to shutter all their older fabs and streamline their operations.
  • Reply 16 of 18
    nr9nr9 Posts: 182member
    Quote:

    Originally posted by Telomar

    I never stated layout would effect performance all I stated is there were some sizable differences between the 90 nm processor and the 130 nm PPC970. What they are will become apparent after release.



    As for SSOI I wouldn't count on seeing it being used just yet.




    well ibm says their 90nm have ssoi



    soi itself reduces leakage a lot.



    do u care to elaborate on what architectural changes the 90nm 970 has?
  • Reply 17 of 18
    telomartelomar Posts: 1,804member
    Quote:

    Originally posted by Nr9

    well ibm says their 90nm have ssoi



    heh. That's news to me. It will however use low-k dielectrics finally.



    Quote:

    Originally posted by Nr9

    soi itself reduces leakage a lot.



    The 130 nm process uses SOI already.



    Quote:

    Originally posted by Nr9

    do u care to elaborate on what architectural changes the 90nm 970 has?



    Not really but it'll be readily apparent at release.
  • Reply 18 of 18
    nr9nr9 Posts: 182member
    Quote:

    Originally posted by Telomar

    heh. That's news to me. It will however use low-k dielectrics finally.



    The 130 nm process uses SOI already.



    Not really but it'll be readily apparent at release.




    appleinsider says they will use ssoi. low-k dielectric mainly reduce capacitance and so prop delay.



    my point was tat mac already have ssoi so already low leakage.



    i have never seen any indication on any website hat the 90nm 970 has architectural improvements.
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