Processor pipelines

luca

I was talking with a friend today about processor pipelines, and how everyone (including Apple) is increasing them like there's no tomorrow. The PowerPC 7400/7410 has a mere 4-stage pipeline. The 745x, aka G4e, has a 7-stage pipeline. The G5 has a much longer 16-stage pipeline.



Meanwhile, Intel's Pentium III had a 10-stage, which moved to the Pentium 4's 20-stage, and now the Prescott's 30-stage. Each revision was slower than the previous one at equal clock speed.



So, I wonder... how much of an effect does the number of pipeline stages actually have on performance? As far as I've heard, the progression from the G4 to the G4e to the G5 has signaled a reduced speed at equal clock speed for each revision. I think pipeline stages make the processor able to operate at a greater frequency, thus making up for the speed hit, but the higher the frequency, the hotter and more power consuming a processor is. This in turn makes it more difficult for the processors to work in laptops, and results in the gigantic 10 lb laptops that Dell has, and in the huge wind tunnel case that the G5 has to use.

whisper

A pipeline only slows things down when there's a stall or the Branch Prediction Unit is wrong. How often does this happen? It depends on the code. I'm sure there's a roughly average frequency out there somewhere, but I don't know what it is or where to find it.

dobby

I have always equated pipeline to lanes on a motorway. Edit (as explained to me by Dan Dobberpuhl alpha chip engineer extrodinare)

You can have lots of lanes at lower speed or much few pipes with faster speed. Both have tradeoffs.



Dobby.

chych

The analogy I've heard is that if the G4s were "short" and "wide", where the Pentiums are "long" and "narrow", the G5 can be described as "long" and "wide". Perhaps this indicates a much greater bandwidth for the G5?

silentechoes

You should check out Ars articles on CPU piplines. Excellent reads, Though fairly technical.

wmf

The bottom line is that the processor designers actually do know what they're doing. They worry about it so you don't have to.

splinemodel

Quote:

Originally posted by wmf

The bottom line is that the processor designers actually do know what they're doing. They worry about it so you don't have to.

Best post of the day.



Shorter pipelines can get clock frequencies higher. If everything is behaving perfectly, then an instruction completes every clock cycle. (or every X clock cycles). There are delays and such, and comp arch folks spend a lot of time figuring out the best ways to deal with these things.